PCB News - Three key points of PCB electromagnetic compatibility (EMC) design

EMC design in PCB should be a big worry for many electronic hardware engineers. For example: how do you consider EMC when stacking PCBS? Are there the same things to consider when designing an EMC for different layers of boards? Considering that everyone has questions about similar issues, xiaobian there sorted out this article about how to do a good job in EMC design of PCB today, hoping to help you.

First, device layout

In PCB design, from an EMC perspective, there are three main factors to consider: the number of input/output pins, device density and power consumption.

A practical rule is that the chip covers 20% of the substrate and consumes no more than 2W of power per square inch.

In terms of device layout, devices related to each other should be as close as possible in principle, digital circuit, analog circuit and power circuit should be placed separately, and high frequency circuit and low frequency circuit should be separated.

Devices that are prone to noise, small current circuits, and large current circuits should be far away from logic circuits. M

ajor interference and radiation sources such as clock circuits and high frequency circuits should be arranged separately, away from sensitive circuits, and the input and output chips should be located near the I/O exit of the hybrid circuit package.

High-frequency components should shorten the connection as far as possible to reduce the distributed parameters and electromagnetic interference between each other. Components vulnerable to interference should not be too close to each other, and input and output should be far away as far as possible. Oscillators are as close to the clock chip as possible and away from the signal interface and low level signal chip.

The components should be parallel or perpendicular to one side of the substrate, so that the components are arranged in parallel as far as possible, which will not only reduce the distributed parameters between components, but also conform to the manufacturing process of the hybrid circuit, making it easy to produce.

The power and ground lead-off pads on the hybrid circuit substrate shall be arranged symmetrically, evenly distributing many power and ground I/O connections. The mount region of the bare chip is connected to a negative potential plane.

When selecting a multilayer hybrid circuit, the layer-to-layer arrangement of the circuit board changes with the specific circuit, but generally has the following characteristics:

(1) The inner layer of power supply and ground distribution can be regarded as a shielding layer, which can well suppress the inherent common-mode RF interference on the circuit board and reduce the distribution impedance of high-frequency power supply.

(2) The power supply plane and the ground plane in the board should be as close to each other as possible, and the ground plane is generally above the power supply plane. In this way, the interlayer capacitor can be used as the smooth capacitor of the power supply, and the grounding plane can shield the radiation current distributed on the power supply plane.

(3) The wiring layer should be arranged adjacent to the power supply or ground plane as far as possible to produce flux cancellation.

Two, PCB wiring

In circuit design, often only pay attention to improve wiring density, or the pursuit of uniform layout, ignoring the impact of line layout on the prevention of interference, so that a large number of signals radiate into the space to form interference, may lead to more electromagnetic compatibility problems.

Therefore, good wiring is the key to the success of the design.

1, ground layout

The ground wire is not only the potential reference point of the circuit, but also the low impedance circuit of the signal.

The common interference on the ground is the interference caused by the current of the ground loop. To solve this kind of interference problem is equivalent to solving most of the electromagnetic compatibility problems.

The noise on the ground wire mainly affects the ground level of the digital circuit, and the digital circuit is more sensitive to the noise on the ground wire when the output is low.

Interference on ground wire may not only cause circuit misoperation, but also lead to conduction and radiation emission. Therefore, the key to reducing these interference lies in minimizing the impedance of the ground wire as much as possible (for digital circuits, reducing the inductance of the ground wire is especially important).

Note the following points in the layout of ground cables:

(1) According to different power supply voltage, digital circuit and analog circuit respectively set ground wire.

(2) the public ground wire as thick as possible. In the multi-layer thick film process, special ground surface can be set up, which helps to reduce the loop area and reduce the efficiency of the receiving antenna. And can be used as a signal line shielding body.

(3) Comb ground wire should be avoided. This structure makes the signal backflow loop very large, which will increase radiation and sensitivity, and the common impedance between chips may also cause circuit misoperation.

(4) when a plurality of chips are installed on the board, there will be a larger potential difference on the ground wire. The ground wire should be designed into a closed loop to improve the noise tolerance of the circuit.

(5) a circuit board with both analog and digital functions, analog ground and digital ground are usually separated and connected only at the power supply.

2. Layout of power supply circuit

In general, except for interference caused directly by electromagnetic radiation, electromagnetic interference caused by power line is common. Therefore, the layout of the power cord is also important, and the following rules should generally be followed.

(Power processing)

(1) The power line is as close to the ground wire as possible to reduce the power supply loop area, and the differential mode radiation is small, which helps to reduce circuit interference. Do not overlap the power supply loops of different power supplies.

(2) When using multi-layer process, analog power supply and digital power supply are separated to avoid mutual interference. Do not place digital and analog power supplies on top of each other, otherwise coupling capacitance will occur and the separation will be destroyed.

(3) Complete dielectric isolation can be used between the power supply plane and the ground plane. When the freq

uency and speed are very high, medium slurry with low dielectric constant should be selected. The power plane should be close to and under the grounding plane to shield the radiation current distributed on the power plane.

(4) Decoupling should be carried out between the power pin and ground pin of the chip. The chip capacitor of 0.01uF should be used for decoupling capacitor, which should be installed close to the chip, so that the circuit area of decoupling capacitor can be reduced as much as possible.

(5) When selecting patch chip, try to choose the chip whose power pin and ground pin are close to each other, which can further reduce the power supply loop area of decoupling capacitor and is conducive to electromagnetic compatibility.