PCB News - Summary of excellent experience of DDR2 PCB Layout

PCB stackup:
For a six-layer board, the general stacks are top, GND, singnal2, singnal3, POWER, and bottom. Generally, it is better to use GND as the reference plane for the signal. The impedance of the trace is determined by the width of the trace, the thickness of the copper foil of the trace, the distance from the trace to the reference plane, the thickness of the copper foil of the reference plane and the board dielectric material. The PCB design should comply with the impedance design requirements of the CPU manufacturer to set the stack. Floor. General PCB design software can also calculate impedance. After finding the PCB manufacturer and knowing the material of the sheet dielectric thickness, you can design the stack and line width by yourself. The address/command signal and the control signal can use the 1.8V memory working voltage as the reference plane. But a complete power plane must be referenced.

Trace length control:
For high-frequency signals such as DDR2, the trace length should be calculated to the CPU core, which introduces a concept called package length. The silicon wafer is etched into a CPU core by physical and chemical methods, and then the CPU core is packaged on a small PCB substrate to become our common CPU. The trace length from the pins on that small PCB board to the CPU core is called the package length, also called PIN delay.
The length of the clock to the same rank memory should be controlled within plus or minus 5 mils.
The length of all traces in the same data group should be controlled within the range of plus or minus 20 mils of the data strobe signal DQS. The length can be different between different data groups, but it should be controlled within plus or minus 500 mils of the clock signal.
The address/command group signal length control is not particularly strict. INTEL Atom N450 requires the control of the clock signal within minus 500 mil to plus 1000 mil. That is to say, the difference between the longest and shortest signal can be 1500mil, but it is better to reduce the signal length difference as much as possible when wiring. There is no problem when the signal lengths of these groups are completely equal when wiring, but it takes up a lot of PCB space and takes a lot of time. If the length of the address/command signal exceeds several thousand mils of the clock signal, it needs to be adjusted in the BIOS firmware. The control is within the scope of the CPU requirements. When onboard memory is needed, only the memory SPD needs to be configured.
The control group signal length control requirements are similar to the address/command group signal requirements. The design should be done in accordance with the requirements of the CPU manufacturer. The INTEL Atom N450 requires the clock signal to be controlled within 0mil to plus 1000mil.
Trace spacing:
Generally speaking, the wiring should be routed according to the 3W principle, that is, the line-to-line spacing on the same plane is 3 times the line width. But this is not necessary, the requirement of intel is relatively small. Generally, the spacing of the meandering traces can be 16 to 20 mils, and it can be increased to 30 mils for the clock signal. The distance between the different groups of signals should be appropriately enlarged, which can be more than 20 mils, and the distance between the address/command group and the control group signals can be smaller than 8 mils. The distance between the BGA fan-out areas can be small, and the cables should be routed according to the CPU design requirements after the cables are routed out.
Other POWER routing:
A 20mil line can be used for the VREF trace, and a 0.1uf capacitor should be added to each device.
The VTT trace should be above 135mil, and every four resistors should be connected to a 0.1uf capacitor, and both ends should be connected to a 10uf capacitor.
Point-to-multipoint signals, such as address/command signals, control signals, and clock signals, should be routed in a "T" shape, that is, the chip should be routed up and then branched, and the length should meet the design requirements of the CPU.