PCB News - Experience of hardware layout

Clock line routing

1. No clock wiring on the surface layer or wiring length=<500mil (critical clock surface layer wiring=<200mil); and a complete ground plane must be used for reflow, and the bridge has not been cross-divided or cross-divided.

2. No other wiring passes through the TOP layer of the crystal oscillator and clock drive circuit area; (this is sometimes difficult to satisfy).

3. Avoid other signal lines around the signal line, and meet the 3W principle when necessary (the center distance between the two lines is 3 times the line width). This is generally not considered when laying out data lines or address lines. And focus on timing (equal length).

4. Where possible, the power layer should try to meet the 20h principle: that is, the power layer boundary is 20 times the thickness of the inner shrinkage plate relative to the ground boundary.

**20H rule: Since the electric field between the power layer and the ground layer is changing, electromagnetic interference will be radiated outward from the edge of the board. It is called the edge effect. The power layer can be retracted so that the electric field is only conducted within the ground layer. Taking a H (the thickness of the medium between the power supply and the ground) as a unit, if the shrinkage is 20H, 70% of the electric field can be confined within the grounding edge; if the shrinkage is 100H, 98% of the electric field can be confined.

5. Meet the 3W principle between clocks of different frequencies

**3W rule: In order to reduce the interference between lines, the line spacing should be large enough. When the line center distance is not less than 3 times the line width, 70% of the electric field can be kept without mutual interference, which is called the 3W rule. If you want to achieve 98% of the electric field without interfering with each other, you can use the 10W rule.

6. When the clock signal layer changes and the reflux reference plane also changes, a ground hole is generally placed next to the clock line layer change via hole.

7. The distance between the clock wiring and the I/O interface and the handle bar>=1000mil.

8. The equal length of the clock line and the adjacent plane layer wiring is <=1000mil.

9. The multi-load clock structure should be star-shaped as much as possible. In actual implementation, the equal-length bifurcation method is generally used when walking to the center of the multi-load point.

10. In the SDRAM wiring, the difference between the length of SDCLK and DATA is <=800mil.

11. The typical transmission speed of stripline (middle layer wiring) is 180ps/inch, and the microstrip line (surface wiring) is 140ps/inch.

Interface wiring requirements:

1. Differential wiring rules: parallel and equidistant, same layer, equal length.

2. The network length between the interface transformer and the interface connector is less than 1000mil.

3. Add bridging measures to the reset line across the segmentation.

4. The wiring of the interface circuit should follow the principle of protection first and filtering later.

5. The primary and secondary isolation components such as interface transformers and optocouplers are isolated from each other, and there is no coupling path such as adjacent planes, and the isolation width to the corresponding reference plane is greater than 100mil.

Stacking of boards:

1. The adjacent layer of the component layer is the ground plane, which provides the device shielding layer and the reference plane for the fixed-layer wiring layer.

2. All signal layers are as close as possible to the ground plane.

3. Try to avoid the 2 signal layers directly adjacent to each other.

4. The main power supply is as close as possible to it.

5. Take into account the symmetry of the laminated structure.

Other wiring attention points:

1. The EMC environment between the power layer and the ground layer is poor, so avoid placing signals that are sensitive to interference.

2. The signal wire must have no right angles.

3. Route the wiring as close to a plane as possible, and avoid cross-segmentation. If it is necessary to cross-segment or cannot be close to the power ground plane, these conditions are only allowed to exist in low-speed signal lines.

Questions about PCB design skills

1. In the EMC test, it was found that the harmonics of the clock signal exceeded the standard very seriously, but the decoupling capacitor was connected to the power supply pin. What aspects should be paid attention to in PCB design to suppress electromagnetic radiation?

The three elements of EMC are radiation source, transmission route and victim. The propagation path is divided into space radiation propagation and cable conduction. So to suppress harmonics, first look at the way it spreads. Power supply decoupling is to solve the propagation of conduction mode. In addition, necessary matching and shielding are also required.

2. For a group of buses (address, data, command) to drive multiple (up to 4, 5) devices (FLASH, SDRAM, other peripherals...), which method is used when PCB wiring?

The influence of the wiring topology on the signal integrity is mainly reflected in the inconsistent signal arrival time on each node, and the reflected signal also arrives at a certain node in the same time, which causes the signal quality to deteriorate. Generally speaking, in a star topology, you can control several stubs of the same length to make the signal transmission and reflection delays consistent to achieve better signal quality.

Before using the topology, it is necessary to consider the situation of the signal topology node, the actual working principle and the wiring difficulty. Different buffers have inconsistent effects on signal reflection, so the star topology cannot solve the delay of the data address bus connecting to flash and sdram, and thus cannot ensure the quality of the signal; on the other hand, high-speed signals generally For communication between dsp and sdram, the speed of flash loading is not high, so in high-speed simulation, it is only necessary to ensure the waveform at the node where the actual high-speed signal works effectively, without paying attention to the waveform at the flash; star topology is compared with daisy chain and other topologies. In other words, wiring is more difficult, especially when a large number of data address signals use star topology.

3. In PCB design, the ground wire is usually divided into protective ground and signal ground; power ground is divided into digital ground and analog ground. Why should the ground wire be divided?

The purpose of dividing the ground is mainly for EMC considerations, and it is worried that the noise on the digital part of the power supply and the ground will interfere with other signals, especially analog signals through the conduction path. As for the division of signal and protective ground, it is because the consideration of ESD static discharge in EMC is similar to the role of lightning rod grounding in our lives. No matter how you divide it, there is only one land in the end. It's just that the noise emission method is different.

4. Is it necessary to add ground wire shields on both sides when fabricating the clock?

Whether to add a shielded ground wire or not depends on the crosstalk/EMI situation on the board, and if the shielded ground wire is not handled well, it may make the situation worse.

5. How to set the layers of a 4-layer board with powerPCB?

You can set the layer definition to

1:no plane+ component(top route)

2: cam plane or split/mixed (GND)

3:cam plane or split/mixed (power)

4: no plane+component (if a single-sided component can be defined as no plane+route)

SDRAM principle design and layout rules

Compared with the traditional SDRAM interface circuit. Registered SDARM circuit has relatively loose design constraints on circuit electrical parameters, and basically does not need to consider the driving ability of the main control chip during design; but because Registered SDRAM is also a higher-speed interface circuit, its circuit design should also follow certain rules to ensure the design The reliability and stability of the circuit.

(1) Principle design rules

1. The phase adjustment capacitor is designed at the clock input end of each chip, and the capacitance value can be set to 10pF, which can be adjusted according to the measured data.

2. At the data pins of each SDRAM chip, design series-connected matching resistors respectively. The matching resistance value can be set to l0Ω.

3. The latch clock of each latch chip adopts different output clocks of the clock expansion circuit.

4. The input clock of each SDRAM chip adopts different output clocks of the clock expansion circuit.

5. The clock output pin of the clock expansion chip is designed to connect a matching resistor in series. The matching resistance value can be set to l0Ω.

6. The output terminal of the latch chip is designed to be connected in series with matching resistance. The matching resistance value can be set to lOΩ.

(2) Wiring rules

1. SDRAM data line: The data signal wiring from MPC824l to the same-SDRAM chip needs to be controlled with equal length, and the length error is controlled within ±5%.

2. SDRAM address/control line: latch the chip to the same-SDRAM

The address/control signal routing of the chip needs to be controlled with equal length, and the length error is controlled within ±5%.

3. The 2-way latch clock output from the clock expansion circuit to the latch chip, and its wiring needs to be controlled with equal length, and the length error is controlled within ±l.27mm.

4. The 4-channel clock output from the clock expansion circuit to the SDRAM chip requires equal length control, and the length error is controlled within ±l.27 mm.

5. The length of the address/control signal from the latch chip to the SDRAM chip is basically the same as the length of the clock trace from the clock expansion circuit to the corresponding SDRAM chip, and the length error is controlled within ±5%.

6. The length of the clock extension circuit feedback clock trace is basically the same length as the average trace length of the clock extension circuit to the SDRAM chip, and the length error is controlled within ±10%.

7. The length of the data line, address line, control line and clock line between MPC824l and SDRAM chip is basically the same length, and the length error is controlled within ±10%.

(3) Layout rules

1. All phase adjustment capacitors are placed close to the receiving end.

2. All clock series matching resistors are placed close to the transmitter.

3. The serial matching resistance of the data pin of the SDRAM chip is close to the SDRAM chip.

4. The serial matching resistance of the output terminal of the latch chip is placed close to the output terminal.

(4) Other design rules

1. Each wiring must be controlled by impedance, that is, single-ended wires are controlled by 50Ω impedance.

2. The power supply pin of the chip must be equipped with a decoupling capacitor, the capacitance value can be 0.1μF. In principle, each power pin must be designed with a decoupling capacitor and placed as close to the power pin as possible.

3. Complete stratum and power layer, at least a complete stratum should be ensured.

4. The clock signal goes to the inner layer as much as possible to reduce EMI.

(5) Debugging of the PCB design

The hardware circuit designed according to the above rules usually only needs to slightly adjust the phase adjustment capacitor value to achieve stable operation under the 100 MHz SDRAM clock. The range of the phase adjustment capacitor value is generally 5~15pF. If the margin of the timing parameters is sufficient, the phase adjustment capacitor may not be welded

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