PCB News - DDR power supply classification

1. Power
   DDR power supplies can be divided into three categories:
   
   The main power supply VDD and VDDQ,
   The main power requirement is VDDQ=VDD, VDDQ is for IO
   VDD is the power supply for buffer power supply, but in general use, VDDQ and VDD are combined into one power supply. Some chips also have VDDL, which supplies power to the DLL, and can use the same power supply as VDD.
   When designing the power supply, it is necessary to consider whether the voltage and current meet the requirements, the power-up sequence of the power supply, the power-up time of the power supply, and the monotonicity.
   The power supply voltage requirement is generally within ±5%.
   The current needs to be calculated according to the different chips used and the number of chips. Since the current of DDR is generally relatively large, when PCB design, if a complete power supply plane is laid on the pins, it is the most ideal state, and the energy storage capacitor is increased at the power inlet, and one is added to each pin. Filter with a small capacitor of 100nF~10nF.

Reference power supply Vref,
The reference power supply Vref is required to follow VDDQ, and Vref=VDDQ/2, so it can be provided by a power supply chip, or it can be obtained by a resistor divider. Since the Vref current is generally small, in the order of several mA to tens of mA, the resistor divider method saves costs and can be more flexible in layout. It is placed closer to the Vref pin and follows closely. VDDQ voltage, so this method is recommended. It should be noted that the resistors used for the voltage divider can be 100~10K, and 1% precision resistors are required.
Each pin of the Vref reference voltage needs to add a 10nF point capacitance filter, and it is better to connect a capacitor in parallel with each voltage divider resistor.

Used for matching voltage VTT (Tracking Termination Voltage)
VTT is the power source pulled up by the matching resistor, VTT=VDDQ/2. In DDR design, depending on the topology, some designs do not use VTT, such as when the controller has fewer DDR devices. If VTT is used, the current requirement of VTT is relatively large, so the wiring needs to be laid with copper. And VTT requires that the power supply can sink current and sink current. Under normal circumstances, you can use a power chip specifically designed for DDR to generate VTT to meet the requirements.
Moreover, a 10Nf~100nF capacitor is generally placed next to each resistor pulled to VTT, and a large uF capacitor is required for energy storage on the entire VTT circuit.
In general, DDR data lines have a one-drive-one topology, and both DDR2 and DDR3 have ODT for matching, so there is no need to pull VTT for matching to get better signal quality. However, if the address and control signal lines are multi-loaded, there will be more than one driver, and there is no ODT inside, and its topology is a T-point structure, so it is often necessary to use VTT for signal quality matching control.

2. Clock
The DDR clock is a differential trace. Generally, a matching method of 100 ohms in parallel with the terminal is used. The control impedance of the differential pair of the differential trace is 100 ohm, and the single-ended line is 50 ohm. It should be noted that the differential line can also use series matching. The advantage of using series matching is that the rising edge of the differential signal can be controlled, which may have a certain effect on EMI.

3. Data and DQS
The DQS signal is equivalent to the reference clock of the data signal, and it needs to be kept at the same length as the CLK signal when routing. DQS is a single-ended signal below DDR2. DDR2 can be used as a differential signal or single-ended. When doing single-ended, you need to connect DQS- to ground, while DDR3 is a differential signal and requires a 100ohm differential line. Due to the internal ODT, DQS does not require a terminal to be connected in parallel with a 100ohm resistor. Each 8bit data signal corresponds to a group of DQS signals.
The DQS signal needs to keep the same length as the DQS signal of the same group when routing, and control the single-ended 50ohm impedance. When writing data, the middle of DQ and DQS are aligned, and when reading data, the edges of DQ and DQS are aligned. DQ signals are mostly one-drive-one, and DDR2 and DDR3 have internal ODT matching, so it is generally sufficient to perform series matching.
4. Address and Control

The address and control signal are not as fast as DQ. They are sampled based on the rising edge of the clock, so they need to be the same length as the clock trace. However, if multiple DDRs are used, the address and control signals are in a one-drive-multiple relationship, and you need to pay attention to whether the matching method is suitable.
5. PCB layout considerations

During PCB layout, DDR particles should be placed as close to the DDR controller as possible. Each power supply pin needs to be placed with a filter capacitor, and the entire power supply needs to have a large capacitor of 10uF or more placed at the power inlet. It is better to use a separate layer for the power supply to be laid on the pins. The resistors for series matching are best placed at the source end. If it is a bidirectional signal, it must be placed at the same end uniformly. If it is a DDR matching structure with multiple drives, the VTT pull-up resistor needs to be placed at the farthest end. Note that the chip layout needs to be balanced. The following figure shows the topological structure of several DDRs. First, in the case of one drive two, it is divided into a tree structure, a daisy chain and a Fly-by structure. Fly-by is a daisy chain structure with a small STUB. The daisy chain structure of DDR2 and DDR3 is more suitable. The tree-like structure allows two chips to be attached to the front and back sides of the PCB to reduce the length of the bifurcation. The DDR topology with more than one drive is more complicated and requires careful simulation.
6. PCB wiring considerations

For PCB layout, use 50 ohm for single-ended traces and 100 ohm for differential traces.
Note that the equal length of the control differential line is within ±10mil, and the same group of lines are also different according to the speed requirements, generally ±50mil.
The control and address lines, DQS lines, and clocks have the same length, and the DQ data lines have the same length as the DQS lines of the same group.
Note that the clock, DQS and other signals should be separated by a distance of more than 3W.
The signals between groups should also be separated by a distance of at least 3W.
It is best to route the same group of signals on the same layer.
Minimize the number of vias.

7. EMI issues
Due to its fast speed and frequent access, DDR needs to consider its external interference in many designs. You need to pay attention to the following points when designing
The principle requires circuit modules and signals that are susceptible to interference, such as analog signals, radio frequency signals, clock signals, etc., as required by performance indicators, so as to prevent DDR from interfering with them and affecting indicators.
Do not use the same power supply for the DDR power supply and other susceptible power modules. If the same power supply must be used, pay attention to the use of inductors, magnetic beads or capacitors for filtering and isolation.
On the clock and DQS signal lines, reserve some places where series resistance and parallel capacitance can be increased. When EMI exceeds the standard, increase the series resistance or capacitance to ground within the range allowed by signal integrity to make the signal rise and delay. Slow down and reduce external radiation.
For shielding, use the shielding structure of the metal shell to shield the external radiation.
Pay attention to maintaining the integrity of the ground.

8. Test Method
Note that the bandwidth of the oscilloscope probe and the oscilloscope itself can meet the test requirements.
The test point should be selected as close as possible to the receiving end of the signal.
Because DDR signaling is more complicated, in order to quickly test, debug, and solve signal problems, we hope to simply separate the read/write bits. At this time, the most commonly used eye diagram analysis is to help check whether the DDR signal meets the voltage, timing, and jitter requirements.
There are several trigger mode settings. First, the leading width trigger can be used to separate the read/write signals. According to the JEDEC specification, the width of the read preamble is 0.9 to 1.1 clock cycles, and the width of the write preamble is specified to be greater than 0.35 clock cycles, and there is no upper limit. The second trigger method is to use a larger signal amplitude trigger method to separate the read/write signal. Usually, the signal amplitude of the read/write signal is different, so we can achieve the separation of the two by triggering the oscilloscope on a larger signal amplitude.
Pay attention to the amplitude of the signal, the frequency of the clock, the cross point of the differential clock, whether the rising edge is monotonous, overshoot, etc. during the test.
The most important thing in timing, the most important thing to pay attention to is the setup time and the hold time.

The above is the introduction of DDR power supply classification. Ipcb is also provided to PCB manufacturers and PCB manufacturing technology.