PCB News - The production and impact of "layer deviation" of PCB production deviation

The production and impact of "layer deviation" of PCB production deviation
Last year, we were so intoxicated in the ocean of technology that we couldn't extricate ourselves, which caused some readers to say that they were too tall and could not understand. At the beginning of the new year, let’s talk about the impact of [size=1em]PCB production on signal quality and product performance. Once any hardware product is designed, it has to be produced. However, in all production, there must be deviations. What are the deviations caused by circuit board production? How big is the deviation? Can product performance accept this deviation? These many problems,
Today, I will talk about one of the many deviations caused by production: "level deviation." Layer deviation refers to the phenomenon of misalignment between the core and the core during the production of different core plates.
The PCB board is laminated with a layer of core and a layer of PP. PP is semi-solid, which is like applying glue on the top and bottom of the paper, and then stacking them one by one. It is impossible to align it 100%., And the glue is fluid, after stacking and pressing again, the paper will slide. The thicker the stack, the larger the overall layer, the effect is shown in the figure below
Let's take a look at the actual PCB situation, such as routing in the GSSG stack (GND layer- Signal layer- Signal layer- GND layer), and the design effect
We study layer bias, the purpose is to study the effect of layer bias on the deterioration of the signal. The following is a very typical case to explain the impact of layer bias.
1. The influence of layer deviation on impedance

Traces often need to pass through dense via areas on the board, such as BGA areas and connector areas. At this time, the distance between the trace and the vias is limited. It is not something you can stay away if you want to stay away. We often say that the wiring here Limited access.
When designing the impedance table, we will indicate the allowable impedance fluctuation range for traces with different line widths and line distances, such as 100ohm+/-10% or 95ohm+/-8%, assuming the design impedance is 100ohm trace Due to the small Dk of the material after pressing, the measured impedance of trace is 105ohm, but according to the design requirements, the impedance of 105ohm does not exceed 100ohm+/-10%, which meets the delivery quality of the factory.
Under the premise of the above 105ohm impedance, the trace passes through the via again, assuming that we lay out it into the original design shown in the figure below during the design stage. We know that the production and processing links will be shifted to the left, or to the right (not what we want), which is completely random. In the design stage, product performance should be considered from the perspective of worst. The following only analyzes the right-side deviation.
The impedance of the original design is 106ohm. If a 5mil layer deviation occurs, the impedance of the trace that enters the anti-pad area of the via fluctuates upward to 108ohm. If in a dense via area (such as BGA), the trace often has to pass through several rows of vias to come out, which will cause the trace impedance to fluctuate frequently, similar to: 106~108~106~108~106. Can your system tolerate frequent 2ohm impedance fluctuations? If your trace impedance has been made to the upper limit of 110 ohm (that is, 100 ohm +10%), add 2 ohm to 110 ohm, can it still be tolerated? Will it affect the yield of the PCB product? ……Worry about these kinds of problems afterwards, it is better to find ways to avoid them in the design stage.