Electronic Design - PCB design and wiring, inspection stage, inspection stage

Digital Model

1, Whether the PCB traces of the digital circuit and the analog circuit are separated, and whether the signal flow is reasonable

2. If the ground is divided for A/D, D/A and similar circuits, do the signal lines between the circuits go from the bridge point between the two grounds (except for differential lines)?

3. The signal line that must cross the gap between the divided power supplies should refer to a complete ground plane.

4. If the stratum design is not divided into divisions, ensure the divisional wiring of digital and analog signals.

Clock and high-speed part

5. Whether the impedance of the PCB high-speed signal line is consistent in all layers

6. Are high-speed differential signal lines and similar signal lines routed in equal length, symmetrical, and parallel to the nearest?

7, make sure that the clock line goes to the inner layer as much as possible

8. Confirm whether the clock line, high-speed line, reset line and other strong radiation or sensitive lines have been wired according to the 3W principle as far as possible

9. Are there any test points for forks on clocks, interrupts, reset signals, 100M/Gigabit Ethernet, and high-speed signals?

10. Is the distance between LVDS and other low-level signals and TTL/CMOS signals within 10H as far as possible (H is the height of the signal line from the reference plane)?

11. Do clock lines and high-speed signal lines avoid passing through dense via areas or routing between device pins?

12. Whether the clock line has met the (SI constraint) requirements (whether the clock signal traces have fewer vias, short traces, and continuous reference planes. The main reference plane should be GND as much as possible; if the main reference plane of GND is changed when changing layers Layers, within 200 mils from the vias are GND vias) If the main reference plane of different levels is changed when changing layers, is there a decoupling capacitor within 200 mils from the vias)?

13, Whether the differential pair, high-speed signal line, and various types of BUS have met (SI constraint) requirements

EMC and reliability

14. For the crystal oscillator, is there a layer of ground under it? Is it avoided that the signal line passes through the device pins? For high-speed sensitive devices, is it possible to prevent signal lines from passing through the device pins?

15 There should be no sharp or right angles on the signal traces of the board (usually turning at a 135 degree angle continuously, and the RF signal line is best to use a circular arc or a cut corner copper foil after calculation)

16, For double-sided boards, check whether the high-speed signal lines are routed close to the return ground wire; for multi-layer boards, check whether the high-speed signal lines are routed as close to the ground plane as possible

17, For the adjacent two-layer signal routing, try to route the wires vertically

18. Avoid signal lines from passing through power modules, common mode inductors, transformers, and filters

19. Try to avoid long-distance parallel routing of high-speed signals on the same layer

20. Are there shielded vias on the dividing edges of the board with digital ground, analog ground, and protective ground? Are multiple ground planes connected by vias? Is the via distance less than 1/20 of the wavelength of the highest frequency signal?

21. Are the signal traces corresponding to surge suppression devices short and thick on the surface?

22. Confirm that there are no islands in the power supply and the stratum, no excessively large slotting, no longer ground plane cracks caused by excessively large through-hole isolation disks or dense vias, no slender strips and narrow passages

23. Are there ground vias placed where there are more signal lines across multiple layers (at least two ground planes are required)

Power and ground

24. If the power/ground plane is divided, try to avoid high-speed signal crossing on the divided reference plane.

25. Confirm that the power and ground can carry enough current. Whether the number of vias meets the load requirements, (estimation method: 1A/mm line width when the outer copper thickness is 1oz, the inner layer 0.5A/mm line width, double the short-line current)

26. For power supplies with special requirements, do they meet the voltage drop requirements?

27. In order to reduce the edge radiation effect of the plane, the 20H principle should be satisfied as much as possible between the power layer and the ground layer. (If possible, the more indented the power layer, the better).

28. If there is land division, does the divided land constitute a loop?

29. Have the power planes of different adjacent layers avoid overlapping placement?

30. Is the isolation between protective ground, -48V ground and GND greater than 2mm?

31, Is the -48V ground only -48V signal return, not connected to other grounds? If you can't, please explain the reason in the remarks column.

32. Is a 10-20mm protective ground placed near the panel with connectors, and double-row staggered holes are used to connect the layers?

33. Does the distance between the power line and other signal lines meet the safety requirements?

PCB forbidden area

34. There should be no traces, copper skins and vias that may cause short circuits under the metal shell components and heat sink components

35. There should be no traces, copper skins and vias around the mounting screws or washers that may cause short circuits

36, Whether there is a trace in the reserved position in the PCB design requirements

37. The distance between the inner delamination line and copper foil of the non-metallized hole should be greater than 0.5mm (20mil), and the outer layer should be 0.3mm (12mil). )

38, copper skin and wire to board edge is recommended to be greater than 2mm and the minimum is 0.5mm

39, 1 ~ 2 mm from the copper skin of the inner stratum to the edge of the board, the minimum is 0.5mm

j. PCB pad wire

84. For two-pad mounted CHIP components (packages of 0805 and below), such as resistors and capacitors, the printed lines connected to the pads should preferably be drawn symmetrically from the center of the pad and printed connected to the pad The lines must have the same width, and this rule can be ignored for lead lines with a line width of less than 0.3mm (12mil)

40. For the pads connected to the wider PCB printed lines, it is better to pass through a narrow printed line in the middle? (Packages of 0805 and below)

41. The circuit should be led out from both ends of the pads of SOIC, PLCC, QFP, SOT and other devices as much as possible