Electronic Design - ​What are the common problems in FPC circuit design?

1. Overlap of pads

A. The overlap of the pads (except the surface mount pads) means the overlap of the holes. During the drilling process, the drill bit will be broken due to multiple drilling in one place, resulting in damage to the hole.

B. Two holes in the multi-layer PCB board overlap. For example, one hole is an isolation disk, and the other hole is a connection pad (flower pad), so that the film will appear as an isolation disk after drawing, resulting in scrap.

Second, the abuse of the graphics layer

A. Some useless connections were made on some graphics layers. Originally, a four-layer PCB was designed with more than five layers, which caused misunderstandings.

B. Save trouble during design. Take the Protel software as an example to draw the lines on each layer with the Board layer, and use the Board layer to mark the line, so that when the light drawing data is performed, the Board layer is not selected, and the board layer is omitted. The connection is broken, or it may be short-circuited due to the selection of the marking line of the Board layer, so the integrity and clarity of the graphics layer is maintained during design.

C. Violation of conventional design, such as the component surface design on the Bottom layer and the welding surface design on the Top, causing inconvenience.

Third, the random placement of characters

A. The SMD soldering pad of the character cover pad brings inconvenience to the on-off test of the printed circuit board and the soldering of the components.

B. The design of the characters is too small, causing difficulties in screen printing, and too large will cause the characters to overlap each other and make it difficult to distinguish.

Four, single-sided FPC pad aperture setting

A. Generally, single-sided pads are not drilled. If the drilled holes need to be marked, the hole diameter should be designed to be zero. If the numerical value is designed, then when the drilling data is generated, the coordinates of the hole appear at this position, and there is a problem.

B. Single-sided pads should be specially marked if they are drilled.

Five, use filler blocks to draw pads

Drawing pads with filler blocks can pass the DRC inspection when designing the circuit, but it is not good for processing. Therefore, the solder mask data cannot be directly generated by the similar pads. When the solder resist is applied, the area of the filler block will be covered by the solder resist, resulting in It is difficult to solder the device.

Sixth, the electrical ground layer is also a flower pad and a connection

Because the power supply is designed as a pattern pad, the ground layer is opposite to the image on the actual printed circuit board. All the connections are isolated lines. The designer should be very clear about this. By the way, you should be careful when drawing isolation lines for several sets of power supplies or grounds, not to leave gaps, short-circuit the two sets of power supplies, and block the connection area (to separate a set of power supplies).

Seven, the processing level is not clearly defined

A. The single-sided board is designed on the TOP layer. If the front and back are not specified, the manufactured board may not be easy to be soldered with components installed.

B. For example, a four-layer PCB board is designed with four layers of TOP mid1 and mid2 bottom, but it is not placed in this order during processing, which requires explanation.

8. There are too many filler blocks in the FPC design or the filler blocks are filled with very thin lines

A. The gerber data is lost, and the gerber data is incomplete.

B. Because the filling block is drawn with lines one by one during light drawing data processing, the amount of light drawing data generated is quite large, which increases the difficulty of data processing.

Nine, the surface mount device pad is too short

This is for continuity testing. For surface mount devices that are too dense, the spacing between the two pins is quite small, and the pads are also quite thin. To install the test pins, they must be staggered up and down (left and right), such as pads. The design is too short, although it does not affect the device installation, but it will make the test pin staggered.

10. The spacing of large-area grids is too small

The edges between the same lines that make up a large area of grid lines are too small (less than 0.3mm). During the manufacturing process of the printed circuit board, the image transfer process is likely to produce a lot of broken films attached to the board after the image is developed, resulting in broken lines .

11. The distance between the large area copper foil and the outer frame is too close

The distance between the large area copper foil and the outer frame should be at least 0.2mm, because when milling the shape, if it is milled to the copper foil, it is easy to cause the copper foil to warp and the solder resist falling off caused by it.

12. The design of the outline frame is not clear

Some customers have designed contour lines in Keep layer, Board layer, Top over layer, etc. and these contour lines do not overlap, which makes it difficult for PCB manufacturers to judge which contour line shall prevail.

13. Uneven graphic design

When pattern plating is performed, the plating layer is uneven, which affects the quality of FPC.

14. When the copper area is too large, grid lines should be used to avoid blistering during SMT.