Electronic Design - QFN pad design guide for PCB board design

1. Basic introduction to QFN package PCB design

QFN (Quad Flat No Lead) is a relatively new form of IC packaging, but due to its unique advantages, its applications have grown rapidly. QFN is a leadless package, which helps reduce the self-inductance between the pins, and has obvious advantages in high-frequency applications. The appearance of QFN is square or rectangular, and the size is close to CSP, so it is very thin and light. The bottom of the component has a welding end that is level with the bottom surface. There is a large exposed welding end in the center for heat conduction. There are I/O welding ends for electrical connection around the periphery of the large welding end. There are two types of I/O welding ends: One type only exposes one side of the bottom of the component, and other parts are encapsulated in the component; the other type has a part exposed on the side of the component on the soldering end.

QFN uses peripheral pins to make PCB wiring more flexible, and the exposed copper soldering end in the center provides good thermal conductivity and electrical performance. These characteristics enable QFN to be reused in some electronic products that require high volume, weight, thermal performance, and electrical performance.

Since QFN is a relatively new form of IC packaging, no relevant content is included in PCB design guidelines such as IPC-SM-782. This article can help guide users in QFN pad design and production process design. However, it should be noted that this article only provides some basic knowledge for reference. Users need to continuously accumulate experience in actual production and optimize the pad design and production process design to achieve satisfactory welding results.

2. QFN package description

The dimensions of QFN can refer to its product manual, which complies with general industry standards. QFN usually adopts JEDEC MO-220 series standard outline, you can refer to these outline dimensions when designing the pad

Three, QFN general PCB design guide

The central bare soldering end and peripheral I/O soldering ends of the QFN form a flat copper lead structure frame, which is then cast in resin to fix it with a mold resin. The exposed central bare soldering end and peripheral I/O soldering end on the bottom surface, All must be soldered to the PCB.

The PCB pad design should be adapted to the actual process capability of the factory in order to obtain the largest process window and obtain good high-reliability solder joints. It should be noted that for the welding of the central bare welding end, through the "anchor" of the component, not only a good heat dissipation effect can be obtained, but also the mechanical strength of the component can be enhanced, which is beneficial to improve the solder joint reliability of the peripheral I/O welding end. The PCB heat dissipation pad designed for the central bare soldering end of the QFN should be designed with a thermal conductive via to connect to the hidden metal layer of the PCB inner layer. This kind of vertical heat dissipation design through the via hole can make the QFN obtain a perfect heat dissipation effect.

Four, QFN pad design guide

1. Peripheral I/O pads

The design of the PCB I/O pad should be slightly larger than the I/O solder end of the QFN, and the inner side of the pad should be designed to be round to match the shape of the solder end

If the PCB has design space, the outer extension (Tout) of the I/O pad is greater than 0.15mm, which can significantly improve the formation of the outer solder joints. If the inner extension (Tin) is greater than 0.05mm, it must be considered between the central heat dissipation pad Leave enough clearance to avoid bridging.

2. Central heat dissipation pad

The central heat-dissipating pad should be designed to be 0-0.15mm larger than each side of the QFN central bare soldering end, that is, the total side length is 0-0.3mm larger, but the central heat-dissipating pad should not be too large, otherwise, it will affect the I/O A reasonable gap between the pads increases the probability of bridging. The minimum gap is 0.15mm, if possible, it is best to be 0.25mm or more.

3. Heat dissipation vias

The heat dissipation vias should be evenly distributed on the central heat dissipation pad with a gap of 1.0mm-1.2mm. The vias should be connected to the metal ground layer of the inner layer of the PCB. The diameter of the vias is recommended to be 0.3mm-0.33mm.

Although increasing the vias (reducing the via gap), it seems that the thermal performance can be improved on the surface, but because increasing the vias also increases the heat return channel, the actual effect is uncertain, and it needs to be determined according to the actual PCB situation (Such as PCB thermal pad size, ground plane).

4. Solder mask design

There are currently two types of solder mask design: SMD (Solder Mask Defined) and NSMD (Non-Solder Mask Defined). SMD: The solder mask opening is smaller than the metal pad; NSMD: The solder mask opening is larger than the metal pad.

Since it is easier to control in the copper corrosion process, the NSMD process is more preferred. Moreover, the SMD process will concentrate the pressure in the overlapping area of the solder mask and the metal layer of the pad, which will easily crack the solder joints under extreme fatigue conditions. The NSMD process makes the solder around the edge of the metal pad, which can significantly improve the reliability of the solder joint.

Due to the above reasons, the NSMD process is generally recommended in the solder mask design of the central heat dissipation pad and peripheral I/O pads. However, the SMD process should be used in the design of the solder mask for the central thermal pad with a relatively large size.

When using the NSMD process, the opening of the solder mask should be 120um-150um larger than the pad, that is, there should be a gap of 60um-75um between the solder mask and the metal pad, and the arc-shaped pad should be designed with a corresponding arc-shaped solder mask. The layer opening is matched, especially at the corners, there should be enough solder mask to prevent bridging.

Each I/O pad should be individually designed with a solder mask opening, so that the adjacent I/O pads can be covered with a solder mask and prevent the formation of bridges between adjacent pads. However, for the I/O pad width of 0.25mm and the fine pitch QFN with a pitch of only 0.4mm, all I/O pads on one side can only be uniformly designed with a large opening, so that the adjacent I/O pads There is no solder mask in between.

Some QFN's central bare soldering end is designed to be too large, so that the gap with the peripheral I/O soldering end is very small, which can easily cause bridging. In this case, the solder mask design of the PCB thermal pad should adopt the SMD process, that is, the solder mask opening should be reduced by 100um on each side to increase the solder mask area between the central thermal pad and the I/O pad .

The solder mask layer should cover the vias on the thermal pad to prevent the solder from being lost from the thermal vias, so that an empty solder can be formed between the central bare soldering end of the QFN and the central thermal pad of the PCB. The diameter of the through-hole solder mask should be 100um larger than the diameter of the via. It is recommended to apply solder mask oil on the back of the PCB to block the via, so that many cavities will be formed on the front heat dissipation pad. These cavities are conducive to the reflow soldering process. The gas is released and larger bubbles are formed around the vias. It should be noted that the existence of these bubbles will not affect the thermal performance, electrical performance and solder joint reliability, which is acceptable.