Electronic Design - The setting of PCB board design wiring constraints

1. Report PCB design parameters

After the layout is basically determined, use the statistical function of the PCB design tool to report basic parameters such as the number of networks, network density, and average pin density to determine the number of signal wiring layers required.

The number of signal layers can be determined by referring to the following empirical data

1. Pin density

2. Number of signal layers

3. The number of layers

Note: PIN density is defined as: board area (square inch)/(total number of pins on board/14)

The specific determination of the number of wiring layers should also consider factors such as the reliability requirements of the single board, the working speed of the signal, the manufacturing cost and the delivery time.

Two, PCB wiring layer settings

In the design of high-speed digital circuits, the power supply and the ground layer should be as close together as possible, and no wiring should be arranged in the middle. All wiring layers are as close as possible to a plane layer, and the ground plane is preferably a wiring isolation layer.

In order to reduce the electromagnetic interference of signals between layers, the signal lines of adjacent wiring layers should be in a vertical direction.

You can design 1-2 impedance control layers according to your needs. If you need more impedance control layers, you need to negotiate with the PCB manufacturer. The impedance control layer should be clearly marked as required. Distribute the network wiring required for impedance control on the board on the impedance control layer.

3. Setting of line width and line spacing

Factors to be considered in the setting of line width and line spacing

A. The density of the veneer. The higher the density of the board, the tendency to use finer line widths and narrower gaps.

B. The current strength of the signal. When the average current of the signal is large, the current that the wiring width can carry should be considered. The line width can refer to the following data:

The relationship between copper foil thickness, trace width and current in PCB design

The current carrying capacity of copper foil of different thickness and width is shown in the following table:

Copper skin thickness 35um Copper skin thickness 50um Copper skin thickness 70um

Copper skin Δt=10 degree Celsius Copper skin Δt=10 degree Celsius Copper skin Δt=10 degree Celsius

Note:

i. When copper is used as a conductor to pass large currents, the current carrying capacity of the copper foil width should be derated by 50% with reference to the value in the table for selection consideration.

ii. In PCB design and processing, OZ (ounces) is commonly used as the unit of copper thickness. 1 OZ copper thickness is defined as the weight of copper foil in 1 square foot area, which corresponds to a physical thickness of 35um; 2OZ copper thickness It is 70um.

C. Circuit operating voltage: the setting of line spacing should consider its dielectric strength.

Input 150V-300V power supply minimum air gap and creepage distance

Input 300V-600V power supply minimum air gap and creepage distance

D. Reliability requirements. When reliability requirements are high, wider wiring and larger spacing tend to be used.

E. PCB processing technology limitations

Domestic and international advanced level

Recommended minimum line width/spacing 6mil/6mil 4mil/4mil

Limit minimum line width/spacing 4mil/6mil 2mil/2mil

Fourth, the hole setting

4.1, cable hole

The definition of the minimum hole diameter of the finished plate depends on the thickness of the plate, and the plate thickness to hole ratio should be less than 5--8.

The preferred series of apertures are as follows:

Aperture: 24mil 20mil 16mil 12mil 8mil

Pad diameter: 40mil 35mil 28mil 25mil 20mil

Inner thermal pad size: 50mil 45mil 40mil 35mil 30mil

The relationship between plate thickness and minimum aperture:

Board thickness: 3.0mm 2.5mm 2.0mm 1.6mm 1.0mm

Minimum aperture: 24mil 20mil 16mil 12mil 8mil

4.2. Blind and buried vias

Blind vias are vias that connect the surface and inner layers without penetrating the entire board. Buried vias are vias that connect the inner layers and are not visible on the surface of the finished board. For the size settings of these two types of vias, please refer to vias. .

When applying blind hole and buried hole design, you should have a full understanding of the PCB processing process to avoid unnecessary problems for PCB processing, and negotiate with the PCB supplier when necessary.

4.3, test hole

Test holes refer to vias used for ICT testing purposes, which can also be used as via holes. In principle, the aperture is not limited, the diameter of the pad should be no less than 25mil, and the center distance between the test holes should not be less than 50mil.

It is not recommended to use component solder holes as test holes.

5. Setting of special wiring section

Special wiring interval means that some special areas on the board need to use wiring parameters that are different from the general settings. For example, some high-density devices need to use finer line widths, smaller pitches, and smaller vias. Or the adjustment of some network wiring parameters, etc., need to be confirmed and set before wiring.

Sixth, define and divide the plane layer

A. The plane layer is generally used for the power supply and ground layer (reference layer) of the circuit. Since different power supplies and ground layers may be used in the circuit, it is necessary to separate the power supply layer and the ground layer. The separation width should consider the potential difference between the different power supplies., When the potential difference is greater than 12V, the separation width is 50mil, otherwise, 20-25mil is optional.

B. Plane separation should consider the integrity of the high-speed signal return path.

C. When the return path of the high-speed signal is damaged, it should be compensated in other wiring layers. For example, a grounded copper foil can be used to surround the signal network to provide a ground return for the signal.