Electronic Design - PCB impedance matching of PCB design skills

Research on impedance matching In PCB design, impedance matching is related to the quality of the signal. Impedance matching technology can be said to be rich and colorful, but how to apply it more reasonably in a specific system requires some factors to be measured. For example, we have designed many source segments that use serial matching in the system.

Why is this method used when matching is needed and in what way. For example: the difference in matching mostly uses terminal matching; clock uses source segment matching; the theoretical starting point of serial terminal matching series terminal matching is that when the signal source impedance is lower than the characteristic impedance of the transmission line, the resistor R is connected in series between the signal source and the transmission line. At the same time, make the output impedance greater than the source end and the characteristic impedance of the transmission line to match, once again suppress the signal reflected from the load end.

After the signal transmission series terminal is matched, it has the following characteristics:

1: Due to the effect of the series matching resistor, the drive signal is transmitted to the load end of its amplitude at 50%.

2: The reflection coefficient of the B signal at the load end is close to +1, so the amplitude of the reflected signal is close to 50% of the original signal amplitude.

3: The reflected signal is superimposed on the signal propagated at the source end, so that the amplitude of the signal received at the load end is approximately the same as the original signal;

4: The reflected signal from the load end propagates to the source end and is absorbed by the matching resistor when it reaches the source end;

When the E reflected signal reaches the source end, the source side drive current drops to 0 until the next signal is sent.

Compared with parallel matching, series matching does not require the signal driver to have a large current drive capability. The principle of selecting series terminals to match the resistance value is simple, that is, the sum of the matching resistance value and the output impedance of the driver is equal to the characteristic impedance of the transmission line. The output impedance of an ideal signal driver is zero, and the actual driver always has a relatively small output impedance, and the output impedance may be different when the signal level changes. For example, the power supply voltage is +4.5V CMOS Drive, the typical output impedance is 37Ω at low power consumption, and the typical output impedance is 45Ω at high power [4]; TTL drive and CMOS drive, its output impedance will change As the signal level changes.

Therefore, it is impossible to provide a very correct matching resistance for TTL or CMOS circuits, which can only be considered in a compromise solution. The signal network of the chain topology is not suitable for matching with series terminals, and all loads must be connected to the end of the transmission line. In a period of time, the signal amplitude at the end of the load is half of the original signal amplitude. Obviously, the signal is in an uncertain logic state, and the noise tolerance of the signal is very low. Series matching is the most commonly used terminal matching method. It has the advantages of low power consumption, no additional DC load on the driver, and no additional impedance between the signal and the ground, and only one resistance element is required.

Parallel terminal matching The theoretical starting point of parallel terminal matching is that when the impedance of the signal source is very small, the input impedance of the load end is matched with the characteristic impedance of the transmission line by increasing the parallel resistance, thereby achieving the purpose of eliminating the reflection at the load end.

The realization form is divided into two forms of single resistance and double resistance. Parallel terminal matched signal transmission has the following characteristics: the driving signal approximately propagates along the transmission line with complete amplitude; all reflections are absorbed by the matching resistor; the signal amplitude received at the load end is roughly the same as the signal amplitude sent by the signal source. In the actual circuit system, the input impedance of the chip is very high, so for the single-resistor form, the parallel resistance value at the load end must be similar to or equal to the characteristic impedance of the transmission line. Assuming that the characteristic impedance of the transmission line is 50Ω, the R value is 50Ω. If the signal has a high level of 5 V, the quiescent current of the signal will reach 100 mA.

Becco uses the small driver capacity of typical TTL or CMOS circuits, and such parallel matching of these circuits rarely occurs in these circuits. Parallel matching of the two-resistor form (also called Davidnan terminal matching) requires a smaller current drive capability than the single-resistor form. This is because the parallel value of the two resistors matches the characteristic impedance of the transmission line, and each characteristic impedance is greater than the characteristic impedance of the transmission line.

In view of the drive capability of the chip, the selection of the two resistance values must follow three principles:

1: The parallel value of the two resistors is equal to the characteristic impedance of the transmission line;

2: The resistance value connected to the power supply should not be too small, so as to avoid the usual drive current is too large and to avoid low-power signals;

3: The resistance value connected to the ground should not be too small to avoid the signal being too large under the normal driving current. The advantage of parallel terminal matching is simple and feasible. The obvious disadvantage is that it will bring DC power consumption: The DC power consumption of a single resistor is closely related to the duty cycle of the signal? Regardless of whether the signal is high or low, the dual resistance mode has DC power consumption. Therefore, it is not suitable for systems with high power consumption requirements, such as battery-powered systems.

In addition, the single-resistance mode does not use a CMOS system due to the general TTL drive capability, while the dual-resistance mode requires two components, which requires PCB board area, so it is not suitable for high-density printed circuit boards. Of course, there are: AC terminal matching, diode voltage clamp and other matching methods.

When the PCB designer sets the characteristic impedance (Z0) of the transmission line itself to 28 ohms, the ground resistance (Zt) of the terminal tube must also be 28 ohms to assist the transmission line to maintain Z0, so that the whole can be stabilized at the ohm design value.

Only when Z0 = Zt is matched, the signal transmission is the most effective, and its "signal integrity" (signal integrity, signal quality for special terms) is also the best.

PCB characteristic impedance (characteristic impedance) 4.1 When the signal is square wave, when the signal line is combined in the transmission line, the high motion position of the positive voltage signal is forward, then from its nearest reference layer (such as the ground layer) theoretically, the electrical field will pass through the accompanying The forward negative pressure signal (equal to the positive pressure signal reverse return path return path) to sense, so as to complete the overall loop (Loop) system. If the "signal" is short to freeze its flight time, it can be imagined that it has been subjected to the instantaneous impedance value (instantaneous impedance) presented by the line, the dielectric layer and the reference layer, which is called the "characteristic impedance".

Therefore, the "characteristic impedance" should be related to line width (w), line thickness (t), dielectric thickness (h) and dielectric constant. nstant (DK) line.