Electronic Design - Detail PCB backflow path of high-speed circuit

1. Basic concepts of reflux

The principle of digital printed circuit board diagram, the transmission of digital signals from a logic gate to another logic gate, the signal through a wire from the output terminal to the receiver, appears to be a one-way flow, many digital engineers therefore believe loop circuits are not related, after all, device driver and receiver are specified as the voltage mode, why also consider current! In fact, the basic circuit theory tells us that the signal is transmitted by electric current, specifically, is the movement of electronic, electron flow is one of the features of electronic never stay anywhere, wherever current flow is bound to come back, so current always flows in the loop, circuits of arbitrary signals in the form of a closed loop. For high frequency signal transmission, it is actually the process of charging the dielectric capacitor sandwiched between the transmission line and the DC layer.

2. Effect of backflow

Backflow is usually accomplished in digital circuits by means of ground and power plane. The backflow path of high frequency signal and low frequency signal is different. Low frequency signal backflow selects impedance path, and high frequency signal backflow selects inductive reactance path.

When the current flows from the driver of the signal through the signal line and into the receiving end of the signal, there is always a return current in the opposite direction: from the ground pin of the load, through the copper-coated plane, to the source of the signal, and the current flowing through the signal line to form a closed loop. The noise frequency caused by the current flowing through the copper-coated plane is equivalent to the signal frequency, and the higher the signal frequency, the higher the noise frequency. The logic gate does not respond to the input signal, but to the difference between the input signal and the reference pin. A single-point terminated circuit responds to the difference between the incoming signal and its logical reference plane, so disturbances in the ground reference plane are equally important as disturbances in the signal path. Logic gates and designated reference input pin pin to respond, we don't know which is specified by the reference pin (for TTL, is usually a negative power, for ECL is usually positive, but not all), in terms of the nature, the anti-interference ability of the differential signal of random noise and power sliding plane has a good effect.

When the PCB board of many digital signal synchronous switch (such as CPU data bus, address bus, etc.), which raises

the transient load current flow from the power circuit or by the circuit into the ground, because the power cord and on the ground impedance, produces the simultaneous switching noise (SSN), on the ground there will be ground plane bounce noise (to play). And when the power line and grounding line on the printed board surround area is larger, their radiation energy is also larger, therefore, we analyze the switching state of digital chip, take measures to control the backflow mode, to reduce the surround area, the purpose of radiation.

Example explanation:

IC1 is the signal output end, IC2 is the signal input end (for the simplified PCB model, it is assumed that the receiving end contains an underlying resistance), and the third layer is the stratum. The land of IC1 and IC2 is derived from the third horizon. The upper right corner of the TOP layer is a power plane connected to the positive pole of the power supply. C1 and C2 are the decoupling capacitors of IC1 and IC2, respectively. The power supply and grounding of the chip shown in the figure are both power supply and ground of the transmitting and receiving signals.

At low frequency, if S1 terminal output high level, the whole current loop is the power supply through the wire to the VCC power plane, and then through the orange path into IC1, and then out of S1 terminal, through the second layer of wire through R1 terminal into IC2, and then into the GND layer, through the red path back to the power negative terminal.

At high frequencies, the distribution characteristics of the PCB can greatly affect the signal. What is often referred to as backflow is a problem frequently encountered in high frequency signals. When S1 to R1 with increasing electric current signal, the external magnetic field changes very fast, can make the conductor near the induction of a reverse current, if the third layer of the ground plane is complete plane, then can produce a blue dashed lines on the ground plane labeling of current, if the power of the TOP layer has a complete plane, There will also be a backflow along the blue dotted line at the TOP layer. Now the signal loop has the current loop, the radiated energy, the ability to couple the external signal. (The skin effect at high frequencies also radiates energy outwards, and the principle is the same.)

Since the high frequency signal level and current change rapidly, but the change period is short, the energy required is not very large, so the chip is powered by the decoupling capacitor close to the chip. When C1 is large enough and the reaction is fast enough (with a very low ESR value, ceramic capacitors are usually used. The ESR of chip capacitors is much lower than tantalum capacitors., the orange path on the top layer and the red path on the GND layer can be regarded as non-existent (there is a current corresponding to the power supply of the whole board, but not the current corresponding to the signal shown).

Therefore, according to the environment constructed in the figure, the entire current path is as follows: positive terminal of C1 - VCC of IC1 -S1-L2 signal line -R1- GND of IC2 - through hole - yellow path of GND layer - through hole - capacitor negative terminal. As you can see, there is a brown equivalent current in the vertical direction of the current, which induces a magnetic field in the middle, and this torus is also easily coupled to external interference. If the signal as shown in the figure is a clock signal, there is a group of 8-bit data lines in parallel, powered by the same power supply of the same chip, the current backflow path is the same. If the data lines are flipped in the same direction at the same time, a large reverse current can be induced on the clock, and this crosstalk can be fatal to the clock signal if the clock lines are not well matched. The intensity of the crosstalk is not proportional to the high or low level of the interference source, but is proportional to the current change rate of the interference source. For a purely resistive load, the crosstalk current is proportional to dI/dt=dV /(T? 10% - 90% * R). In the formula, dI/dt (current change rate), dV(amplitude of the interference source), and R(load of the interference source) refer to the parameters of the interference source (for capacitive load, dI/dt is the same as T? 10% to 90% of the square is inversely proportional.) . It can be seen from the formula that the crosstalk of low-frequency signals is not necessarily smaller than that of high-speed signals. That is, we said: 1KHz signal is not necessarily a low speed signal, to consider the situation of the edge. For a signal with a very steep edge, it contains many harmonics and has a large amplitude at all octaves. Therefore, when selecting devices, we should also pay attention to not blindly choose chips with fast switching speed, which will not only cost high, but also increase crosstalk and EMC problems.

Any adjacent power supply layer or other surface that has appropriate capacitors at both ends of the signal to provide a low reactance path to GND can be used as the backflow surface of the signal.In common applications, the IO power supply of the chip corresponding to the transceiver is often the same, and there are generally 0.01-0.1uF decoupling capacitors between the power supply and the ground, and these capacitors are just at both ends of the signal, so the backflow effect of the power plane is second only to the ground plane. With the use of other power planes for backflow, there is often no low reactance path to ground at both ends of the signal. In this way, the current induced in the adjacent plane will find the nearest capacitor and return to the ground. If the "near capacitance" is far from the start or end, the backflow will also go through a "long distance" to form a complete backflow path, and this path is also the backflow path of adjacent signals. The same backflow path has the same effect as common ground interference, which is equivalent to crosstalk between signals.

For some unavoidable cross-power splits, high-pass filters made of capacitors or RC series can be connected across the splits (e.g., 10-ohms resistor series 680p capacitors, the specific value depends on their own signal type, that is, to provide a high-frequency backflow path, but also to isolate low-frequency cross talk between mutual planes). This may involve adding capacitors between power planes, which may seem comical, but it certainly works. If some specifications do not allow, capacitance can be drawn to ground separately from the two planes at the split point.

In the case of using other planes to do reflux, several small capacitors can be appropriately added to the ground at both ends of the signal to provide a reflux path. But that is often difficult to achieve. Most of the surface space near the terminal is occupied by the matching resistor and the chip's decoupling capacitor.

Backflow noise is one of the main noises in the reference plane. Therefore, it is necessary to study the path and flow range of the return current.