Electronic Design - What are the precautions for high-speed PCB design

(1) Determination of high-speed signals

The delay per unit inch on the PCB is 0.167ns. However, if there are many vias, many device pins, and many constraints set on the network cable, the delay will increase. Generally, the signal rise time of high-speed logic devices is about 0.2ns. If there are GaAs chips on the board, the maximum wiring length is 7.62mm.

Let Tr be the signal rise time and Tpd be the signal line propagation delay. If Tr≥4Tpd, the signal falls in a safe area. If 2Tpd≥Tr≥4Tpd, the signal falls in the uncertainty region. If Tr≤2Tpd, the signal falls in the problem area. For signals falling in uncertain areas and problem areas, high-speed wiring methods should be used.

(2) Transmission line effect

Based on the above-defined transmission line model, to sum up, the transmission line will bring the following effects to the entire circuit design.

2.1 Reflected signal

If a trace is not properly terminated (terminal matching), then the signal pulse from the driving end is reflected at the receiving end, causing unexpected effects and distorting the signal profile. When the distortion is very significant, it can cause a variety of errors and cause design failure. At the same time, the susceptibility of distorted signals to noise increases, which can also cause design failures. If the above situation is not considered enough, EMI will increase significantly, which will not only affect the results of its own design, but also cause the failure of the entire system. The main reasons for reflected signals are: too long traces; transmission lines that are not terminated by matching, excessive capacitance or inductance, and impedance mismatch.

2.2 Delay and timing errors

Signal delay and timing errors are manifested as: the signal does not jump for a period of time when the signal changes between the high and low thresholds of the logic level. Excessive signal delay may cause timing errors and confusion of device functions. Problems usually arise when there are multiple receivers. The circuit designer must determine the worst-case time delay to ensure the correctness of the design. The reason for the signal delay: the driver is overloaded, and the wiring is too long.

2.3 Multiple times of crossing the logic level threshold error

The signal may cross the logic level threshold many times during the transition process, which leads to this type of error. The error of crossing the logic level threshold multiple times is a special form of signal oscillation, that is, the oscillation of the signal occurs near the logic level threshold, and multiple crossing the logic level threshold will cause the logic function disorder. Causes of reflected signals: long traces, unterminated transmission lines, excessive capacitance or inductance, and impedance mismatch.

2.4 Overshoot and undershoot

Overshoot and undershoot come from two reasons: the trace is too long or the signal changes too fast. Although most component receiving ends are protected by input protection diodes, sometimes these overshoot levels will far exceed the component power supply voltage range and damage components.

(3) Methods to avoid transmission line effects

In view of the influences introduced by the above transmission line problems, let's talk about the methods to control these influences from the following aspects.

3.1 Strictly control the length of key network cables

If there is a high-speed transition edge in the design, the problem of the transmission line effect on the PCB must be considered. Fast integrated circuit chips with very high clock frequencies that are commonly used nowadays have such problems. There are some basic principles to solve this problem: if CMOS or TTL circuits are used for design, the operating frequency is less than 10MHz, and the wiring length should not be greater than 7 inches. The wiring length should not be greater than 1.5 inches at 50MHz. If the operating frequency reaches or exceeds 75MHz, the wiring length should be 1 inch. The maximum wiring length for GaAs chips should be 0.3 inches. If this standard is exceeded, there will be transmission line problems.

3.2 Reasonably plan the topological structure of the wiring

Another way to solve the transmission line effect is to select the correct wiring path and terminal topology. The topological structure of the wiring refers to the wiring sequence and wiring structure of a network cable. When using high-speed logic devices, unless the length of the trace branch is kept short, signals with rapidly changing edges will be distorted by the branch traces on the signal trunk trace. Under normal circumstances, PCB routing uses two basic topologies, namely Daisy Chain routing and Star distribution.

For daisy chain wiring, the wiring starts from the driving end and reaches each receiving end in turn. If a series resistance is used to change the signal characteristics, the position of the series resistance should be close to the drive end. In terms of controlling the high-order harmonic interference of the wiring, the daisy chain wiring has the best effect. However, this wiring method has the lowest distribution rate, and it is not easy to distribute 100%. In the actual design, we make the branch length in the daisy chain wiring as short as possible. The safe length value should be: Stub Delay <= Trt *0.1.

The star topology structure can effectively avoid the asynchronous problem of the clock signal, but it is very difficult to manually complete the wiring on the high-density PCB board. Using an automatic router is the best way to complete star wiring. Terminating resistors are required on each branch. The resistance of the terminal resistor should match the characteristic impedance of the connection. This can be calculated manually or by CAD tools to calculate the characteristic impedance value and the terminal matching resistance value.

The series resistance matching terminal will not produce additional power consumption, but will slow down the signal transmission. This method is used for bus drive circuits where the time delay has little effect. The advantage of the series resistance matching terminal is that it can reduce the number of on-board devices and the density of wiring.

The last method is to separate the matching terminal. In this way, the matching component needs to be placed near the receiving end. The advantage is that it will not pull down the signal, and noise can be avoided very well. Typically used for TTL input signals (ACT, HCT, FAST).

In addition, the package type and installation type of the terminal matching resistor must also be considered. Generally, SMD surface mount resistors have lower inductance than through-hole components, so SMD packaged components become the first choice. If you choose ordinary in-line resistors, there are also two options for installation: vertical and horizontal.

In the vertical installation mode, one mounting pin of the resistor is very short, which can reduce the thermal resistance between the resistor and the circuit board, so that the heat of the resistor can be more easily dissipated into the air. But a longer vertical installation will increase the inductance of the resistor. Horizontal installation has lower inductance due to lower installation. However, the overheated resistance will drift. In the worst case, the resistance will become an open circuit, causing the PCB trace termination matching failure and becoming a potential failure factor.

3.3 Methods to suppress electromagnetic interference

A good solution to the signal integrity problem will improve the electromagnetic compatibility (EMC) of the PCB board. One of the very important is to ensure that the PCB board has a good grounding. It is very effective to use a signal layer with a ground layer for complex designs. In addition, minimizing the signal density of the outermost layer of the circuit board is also a good way to reduce electromagnetic radiation. This method can be realized by using the "surface area layer" technology "Build-up" design and manufacturing PCB. The surface area layer is realized by adding a combination of a thin insulating layer and micro-holes used to penetrate these layers on a common process PCB. The resistance and capacitance can be buried under the surface layer, and the trace density per unit area will be nearly doubled. Reduce the size of the PCB. The reduction of PCB area has a huge impact on the topology of the trace, which means that the current loop is reduced, the length of the branch trace is reduced, and the electromagnetic radiation is approximately proportional to the area of the current loop; at the same time, the small size feature means high density of lead Foot-packaged devices can be used, which in turn reduces the length of the wire, thereby reducing the current loop and improving the electromagnetic compatibility characteristics.

In summary, the above is the design of high-speed circuit boards.