ATE Load board PCB

Ate testing is inseparable from the design of ATE interface board. A good probe card / load board basically ensures the success of mass production. Generally speaking, the ATE test engineer is responsible for the requirements definition of the board and some schematic design. The PCB layout and wiring are handed over to professional PCB vendors. The test engineer is responsible for the review of each design result.

Complex SoC products such as CPU/GPU/APU.... Have very high power when working at full speed, and the power supply voltage decreases with the process evolution (the working voltage of digital core with TSMC 7Nm is 0.7), so the design of PDN is very demanding. The equivalent impedance of the PDN must be small and flat throughout the frequency domain to ensure that the sudden change in current does not result in a large voltage drop:

The impedance design of a PDN is essentially how to add a block/decoupling capacitors:

The first thing you need to know is the capacitors of one-dies and on-packages, a general design layout that you can extract later. These capacitors (about 1uf) ensure that the impedance of the PDN is small in high frequency region, which cannot be improved by PCB design.

The internal resistance and inductance of the power supply in the low frequency region determine the impedance of the PDN to a certain extent, which can be improved by placing a large tantalum capacitance near the power input end.

Many different decoupling capacitors need to be placed near the DUT power pin to ensure flat PDN impedance between 10Khz and 10Mhz.

Note: The capacitance between power layers and GND layers is a good decoupling capacitors (several nf), which can be increased by reducing the layer spacing and high media parameters;

VIA Design Issues

When it comes to PDN design, the VIA of decoupling capacitors needs to give special consideration to inductance. When checking PCB, you need to check the pad and VIA position of each device to avoid the inductance increase caused by redundant traces.

Impedance Continuity of High Speed Signals

Any VIA, pogo pad, and components on a high-speed signal track will cause impedance discontinuities; VIA of RX and TX can cause cross talk problems; The process control precision of PCB vendor will result in poor actual impedance...

For example, ground voiding is used to increase the equivalent impedance of microstrip by digging out the grounds to solve the difference between strip trace and microstrip impedance.

Questions of the Commons

Digital, analog, RF ground. All kinds of places end up in a star connection near the DUT, don't move the single point connection away from the DUT.

Laminated design

The traditional design reduces the inductance of VIA by placing RF/mix-signal near the top/bottom layer. Placing the power layer in the center reduces EMI issues, as shown in the following figure.

In addition, the digital power supply and digital signal layer, preferably away from analog/RF ground and analog/RF signals, to avoid interference. Therefore, the DPS layer adjacent to the ANALOG GND is best to allocate a power supply with small current and current variation.

For high power low voltage devices such as CPU/GPU, the DPS layer should be placed on top to reduce VIA and improve PDN. The price, of course, is that decoupling caps must be placed under sockets, not at the bottom level.

The problem of bottom noise

High-precision ADC/DAC has a high requirement for bottom noise of the board. If the direct use of ATE power supply will result in a high bottom noise, consider using ultra-low noise LDO for power supply.

At the same time, the analog input of ADC, the analog output of DAC can be fencing shielding surrounded by analog ground, and the analog ground of shielding needs to place VIA along the analog trace interval.

Selection of PCB Material

FR4 is a commonly used PCB dielectric material, but for high-speed signals, its insertion loss is larger, so it may be necessary to choose other materials. If a PCB is mixed with different dielectric materials, the problems caused by different thermal expansion and cooling coefficients of different materials need to be considered.