PCB Technical - EMI solutions in the design of multi-layer PCB circuit boards

Power bus

Properly placing a capacitor of appropriate capacity near the power supply pin of the IC can make the IC output voltage jump faster. However, the problem does not end here. Due to the limited frequency response characteristics of capacitors, the capacitors cannot generate the harmonic power required to drive the IC output cleanly in the full frequency band. In addition, the transient voltage formed on the power bus will cause a voltage drop across the inductor of the decoupling path, and these transient voltages are the main common mode EMI interference sources. How should we solve these problems?

As far as the IC on our circuitboard is concerned, the power layer around the IC can be regarded as an excellent high-frequency capacitor, which can collect the part of the energy leaked by the discrete capacitor that provides high-frequency energy for clean output. In addition, the inductance of a good power layer should be small, so the transient signal synthesized by the inductance is also small, thereby reducing common mode EMI.

Of course, the connection between the power layer and the IC power pin must be as short as possible, because the rising edge of the digital signal is getting faster and faster, and it is best to connect it directly to the pad where the IC power pin is located. This needs to be discussed separately.

In order to control common-mode EMI, the power plane must help decoupling and have a sufficiently low inductance. This power plane must be a well-designed pair of power planes. Someone may ask, how good is good? The answer to the question depends on the layering of the power supply, the materials between the layers, and the operating frequency (that is, a function of the rise time of the IC). Normally, the power layer spacing is 6mil, and the interlayer is FR4 material, the equivalent capacitance per square inch of the power layer is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance.

There are not many devices with a rise time of 100 to 300 ps, but according to the current IC development speed, devices with a rise time in the range of 100 to 300 ps will occupy a high proportion. For circuits with a rise time of 100 to 300ps, 3mil layer spacing will no longer be suitable for most applications. At that time, it was necessary to adopt layering technology with a layer spacing of less than 1 mil, and to replace FR4 dielectric materials with materials with high dielectric constants. Now, ceramics and ceramic plastics can meet the design requirements of 100 to 300 ps rise time circuits.

Although new materials and new methods may be used in the future, for today's common 1 to 3ns rise time circuits, 3 to 6mil layer spacing and FR4 dielectric materials, it is usually sufficient to handle high-end harmonics and make the transient signal low enough, that is to say, Common mode EMI can be reduced very low. The PCB layered stacking design examples given in this article will assume a layer spacing of 3 to 6 mils.

Electromagnetic shielding

From the perspective of signal traces, a good layering strategy should be to put all signal traces on one or several layers, and these layers are next to the power layer or ground layer. For the power supply, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible. This is what we call the "layering" strategy.

PCB stacking

What stacking strategy helps to shield and suppress EMI? The following layered stacking scheme assumes that the power supply current flows on a single layer, and the single voltage or multiple voltages are distributed in different parts of the same layer. The case of multiple power layers will be discussed later.

4-layer board

There are several potential problems with the 4-layer board design. First of all, the traditional four-layer board with a thickness of 62 mils, even if the signal layer is on the outer layer, and the power and ground layers are on the inner layer, the distance between the power layer and the ground layer is still too large.

If the cost requirement is first, you can consider the following two traditional 4-layer board alternatives. Both of these solutions can improve the performance of EMI suppression, but they are only suitable for applications where the component density on the board is low enough and there is enough area around the components (place the required power supply copper layer).

The first is the preferred solution. The outer layers of the PCB are ground layers, and the middle two layers are signal/power layers. The power supply on the signal layer is routed with a wide line, which can make the path impedance of the power supply current low, and the impedance of the signal microstrip path is also low. From the perspective of EMI control, this is the best 4-layer PCB structure available. In the second scheme, the outer layer uses power and ground, and the middle two layers use signals. Compared with the traditional 4-layer board, the improvement is smaller, and the interlayer impedance is as poor as the traditional 4-layer board.

If you want to control the trace impedance, the above stacking scheme must be very careful to arrange the traces under the power and ground copper islands. In addition, the copper islands on the power supply or ground layer should be interconnected as much as possible to ensure DC and low-frequency connectivity.

6-layer board

If the density of components on a 4-layer board is relatively high, a 6-layer board is best. However, some stacking schemes in the 6-layer board design are not good enough to shield the electromagnetic field, and have little effect on the reduction of the transient signal of the power bus. Two examples are discussed below.

In the first example, the power supply and ground are placed on the 2nd and 5th layers respectively. Due to the high copper impedance of the power supply, it is very unfavorable to control the common mode EMI radiation. However, from the point of view of signal impedance control, this method is very correct.

In the second example, the power supply and ground are placed on the 3rd and 4th layers respectively. This design solves the problem of power supply copper impedance. Due to the poor electromagnetic shielding performance of the 1st and 6th layers, the differential mode EMI is increased. If the number of signal lines on the two outer layers is the smallest and the trace length is very short (shorter than 1/20 of the wavelength of the highest harmonic of the signal), this design can solve the differential mode EMI problem. Fill the copper-clad area with no components and no traces on the outer layer and ground the copper-clad area (every 1/20 wavelength as an interval), which is particularly good at suppressing differential mode EMI. As mentioned earlier, it is necessary to connect the copper area with the internal ground plane at multiple points.

General-purpose high-performance 6-layer board design Generally, the first and sixth layers are laid out as ground layers, and the third and fourth layers are used for power and ground. Since there are two double microstrip signal line layers in the middle between the power layer and the ground layer, the EMI suppression capability is excellent. The disadvantage of this design is that there are only two routing layers. As mentioned earlier, if the outer traces are short and copper is laid in the traceless area, the same stacking can also be achieved with a traditional 6-layer board.

Another 6-layer board layout is signal, ground, signal, power, ground, signal, which can realize the environment required for advanced signal integrity design. The signal layer is adjacent to the ground layer, and the power layer and the ground layer are paired. Obviously, the disadvantage is the unbalanced stacking of layers.

This usually brings trouble to manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. After the copper is filled, if the copper density of the third layer is close to the power layer or ground layer, this board can not be strictly counted as a structurally balanced circuit board . The copper-filled area must be connected to power or ground. The distance between the connection vias is still 1/20 wavelength, and it may not be necessary to connect everywhere, but it should be connected under ideal circumstances.

10-layer board

Since the insulating isolation layer between the multilayer boards is very thin, the impedance between the 10 or 12 layers of the circuit board is very low. As long as there is no problem with the layering and stacking, excellent signal integrity can be expected. It is more difficult to manufacture 12-layer boards with a thickness of 62mil, and there are not many manufacturers that can process 12-layer boards.

Since there is always an insulating layer between the signal layer and the loop layer, the solution of assigning the middle 6 layers to route the signal lines in a 10-layer board design is not the best. In addition, it is important to make the signal layer adjacent to the loop layer, that is, the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, and signal.

This design provides a good path for the signal current and its loop current. The proper wiring strategy is to route the wires in the X direction on the first layer, the Y directions on the third layer, and the X directions on the fourth layer, and so on. Looking at the routing intuitively, the first layer 1 and the third layer are a pair of layered combinations, the 4th and 7th layers are a pair of layered combinations, and the 8th and 10th layers are the last pair of layered combinations. When it is necessary to change the routing direction, the signal line on the first layer should be transferred to the third layer through the "via" and then change the direction. In fact, it may not always be possible to do this, but as a design concept, it must be followed as much as possible.

Similarly, when the signal routing direction changes, it should go from the 8th and 10th layers or from the 4th to the 7th layer through vias. This wiring ensures the tightest coupling between the forward path of the signal and the loop. For example, if the signal is routed on the first layer and the loop is routed on the second layer and only on the second layer, then the signal on the first layer is transferred to the third layer through the "via". The loop is still on the second layer, so as to maintain the characteristics of low inductance, large capacitance and good electromagnetic shielding performance.

If the actual wiring is not like this, what should I do? For example, the signal line on the first layer goes through the via hole to the 10th layer. Ground pins of components such as resistors or capacitors). If there happens to be such a via nearby, you are really lucky. If there is no such close via hole available, the inductance will become larger, the capacitance will be reduced, and the EMI will definitely increase.

When the signal line must leave the current pair of wiring layers to other wiring layers through vias, ground vias should be placed nearby the vias so that the loop signal can return to the proper grounding layer smoothly. For the layered combination of the 4th and 7th layers, the signal loop will return from the power layer or the ground layer (that is, the 5th or 6th layer), because the capacitive coupling between the power layer and the ground layer is good, and the signal is easy to transmit .

Multi-power layer design

If the two power layers of the same voltage source need to output large currents, the circuit board should be laid out into two sets of power layers and ground layers. In this case, an insulating layer is placed between each pair of power and ground layers. In this way, we get the two pairs of power bus bars with equal impedances that divide the current we expect. If the stacking of the power layers causes the impedance to be unequal, the shunt will not be uniform, the transient voltage will be much larger, and the EMI will increase sharply.

If there are multiple power supply voltages with different values on the circuit board, multiple power supply layers are required accordingly. Remember to create their own paired power supply and ground layers for different power supplies. In the above two cases, when determining the position of the paired power layer and ground layer on the circuit board, keep in mind the manufacturer's requirements for the balanced structure.

Summary

In view of the fact that most of the circuit boards designed by engineers are traditional printed circuit boards with a thickness of 62 mils and no blind or buried vias, the discussion of circuit board layering and stacking in this article is limited to this. For circuit boards with large differences in thickness, the layering scheme recommended in this article may not be ideal. In addition, the processing process of the circuit board with blind holes or buried holes is different, and the layering method in this article is not applicable.

The thickness, via process and the number of layers of the circuit board in the circuit board design are not the key to solving the problem. Excellent layered stacking is to ensure the bypass and decoupling of the power bus, and minimize the transient voltage on the power layer or ground layer. And the key to shielding the electromagnetic field of the signal and power supply. Ideally, there should be an insulating isolation layer between the signal routing layer and the return ground layer, and the paired layer spacing (or more than one pair) should be as small as possible. Based on these basic concepts and principles, a circuit board that can always meet the design requirements can be designed. Now that the rise time of IC is very short and will be shorter, the technology discussed in this article is essential to solve the problem of EMI shielding.