Modern IC amplifiers with extremely low harmonic distortion can improve dynamic range in a range of applications. However, pay special attention to the layout of these amplifiers on the printed circuit board, because improper printed circuit board layout can deteriorate the distortion performance by 20dB.
A typical high-speed amplifier structure includes two sets of bypass capacitors. The capacitance of one set of capacitors is larger (about 1mF to 10mF), and the other set is several orders of magnitude smaller (1nF to 100nF). These capacitors can provide a low impedance ground path at frequencies where the amplifier's power attenuation is relatively low. The correct bypass of a high-speed amplifier usually requires two or more sets of capacitors, because before the upper limit of the amplifier bandwidth, a capacitor bank with a larger capacitance will generally self-resonate. High-quality chip capacitors are ideal decoupling capacitors because they have much lower inductance than through-hole capacitors.
The resistor RT is used to terminate the input of the amplifier to match the source impedance with the impedance of the test instrument used for the measurement. In application circuits that do not use transmission lines, termination resistors are not required. The output drive load of the amplifier in the figure is RL, and RL represents any possible load to be driven by the amplifier. When the output voltage of the amplifier is positive,
the amplifier must provide current for RL. Similarly, when the output voltage is negative, the amplifier must sink current. Whether the amplifier absorbs current through the load or provides current to the load, there must be a path for the current to return to the power supply. When the current returns, the channel with the lowest impedance will be selected.
In the case of high frequency, the lowest impedance path is through the bypass capacitor. When the amplifier supplies or absorbs high-frequency current, the current flows through multiple loops. The ground terminal of the upstream bypass capacitor provides current for the op amp, and the absorption current of the op amp is grounded through the downstream bypass capacitor. Each high-frequency current flowing through the bypass capacitor is half-wave rectified. The key to effective bypass is to understand how high-frequency current flows.
The circuit shown includes a high-speed amplifier that drives an equivalent 1kΩ load. The load forms an attenuator, and a 50Ω reverse termination is required for testing. The input is also terminated to 50Ω to match the signal source used. The distortion measurement results vary for different circuit board layouts. Analyzing the high-frequency current loop of the circuit layout will help clarify the differences in these second harmonic distortions.
It means a worse situation. The power supply is located on the back of the PCB circuit board, which means that the bypass capacitor must be connected to the power supply by a through hole (a through hole from one layer of the printed circuit board to another layer). These vias increase the inductance of the high-frequency current loop. When the amplifier absorbs current, it returns to C2 and C4 through a solid ground plane. However, when the amplifier provides current, the current must pass through two sets of inductive vias before returning to C1 and C3.
At high frequencies, these inductances can add considerable impedance. When high-frequency current passes through these impedances, an error voltage is generated. Since the high frequency current is half-wave rectified, the error voltage is also half-wave rectified. The half-wave rectified signal carries a large number of odd harmonic components, which will cause second harmonic distortion, while the third harmonic remains unchanged.
On the contrary, it is an improved layout. The power supply is bypassed on the front side of the circuit board, so the bypass capacitor does not need to use through holes. In addition, the load ground is close to the two decoupling networks, so there is no need for a through hole on the channel where the amplifier supplies and absorbs high-frequency current. This improved printed circuit board layout method improves the second harmonic distortion index by 3dBc to 18dBc. And this improvement is applicable to various frequencies.
Differential bypass
The bypass method is useful to avoid grounding problems. It can be modified so that one set of bypass capacitors (C1 and C3) are connected across the power supply, while the other set of bypass capacitors (C2 and C4) are still connected between the power supply and ground.
This structure can conveniently realize the true grounding of the bypass capacitor and the load on the printed circuit board. The complete grounding of the load and the bypass capacitor can minimize the inductance between the two grounding points, thereby reducing the error voltage formed by the high-frequency ground current. In addition, the high-frequency current is integrated before returning to the load or entering the load, and there will be no half-wave rectification problems in the case of standard bypass, and it will hardly contain odd harmonic components. Therefore, the error voltage generated in the current channel does not increase distortion.
Applying this technique to a PCB layout with poor bypass can significantly improve distortion. Keep in mind that the bypass capacitor trace should be as short as possible and try not to use vias. When using vias, keep in mind that the inductance of two parallel vias is only half of the inductance of a single via. When the diameter of the through hole is increased, the inductance of the through hole will also decrease. This method has proven to be particularly useful when the feedback network needs to be grounded and the closed-loop gain is greater than one. In this case, the feedback network is an effective part of the amplifier's load. The high-frequency current flowing through the feedback network also returns to the power supply through the bypass capacitor. Therefore, it is also necessary to determine the grounding method of the feedback network to minimize the increase in inductance of the bypass capacitor.