PCB Technical - Offset source in high-speed PCB

The following is the analysis and solution of the offset source in high-speed PCB, I hope it will be helpful to everyone.

Signal synchronization in high-speed digital devices relies on accurate switching measurements from digital ICs. There are many factors that affect the signal switching time, and wrong estimation will increase the bit error rate of the device. In devices without redundancy, a higher bit error rate may cause the PCB to stop functioning.

1. Signal rise/fall time and skew

Digital ICs have some output capacitance and characteristic impedance, which cause delays when switching between switch states. The rise and fall times of the signal are usually approximately linear, but the actual rise and fall times are exponential, similar to the values measured in a simple RC series circuit.

This linear approximation is suitable for lower switching speeds, where the switching period is much longer than the equivalent time constant associated with the rise/fall time. The linear approximation tends to underestimate the switching time. Another approximation is the time required to set the switching speed to transition between the low end of the on state and the high end of the off state.

Unfortunately, both of these approximations may underestimate the proper rise/fall time of the digital signal. This can cause problems when selecting the appropriate switching speed and synchronization signal network.

The effect of signal switching and the skew it produces are twofold. First, it causes an error in the arrival time of the signal transmitted through the continuous IC. Different ICs can produce slightly different output pulse shapes, and the output pulses can be changed according to the precise digital pulse stream. This creates different reference times between signals, which can cause problems when the designer synchronizes high-speed circuits.

Secondly, the exponential rise and fall times during switching can cause the output voltage to fall in the margin or undefined area of the noise. If you try to drive the PCB at a data rate similar to the effective RC time constant, it will increase the bit error rate.

When the data rate is higher than ~100 Mbps, the deviation should be reduced by using a forwarding or embedded clock in the PCB. In most high-speed designs, signals are routed in differential pairs to reduce crosstalk. This requires precise skew compensation between the positive leg and the negative leg of the trace pair in the differential signal network. Before signal degradation becomes a major issue, Gbps data rates or higher data rates may only allow a skew of a few picoseconds.

2. The influence of circuit board substrate and parasitic capacitance

By considering the conductive traces floating in the vacuum, simple simulation can take into account the deviation of the digital signal. A better simulation will consider the presence of the substrate, which creates parasitic capacitance between adjacent conductors. This parasitic capacitance can be viewed as a parallel capacitor, which increases the total capacitance of a given trace. This will increase the effective RC time constant and increase the skew.

As the interconnect density increases, the parasitic capacitance will only increase further. These circuits have tighter spacing between traces, resulting in higher parasitic capacitance. Need to adjust the trace width appropriately to ensure that the trace can be properly impedance matched during the design process.

In a multi-layer PCB, the epoxy resin and glass weave in the PCB substrate will also affect the skew. Due to PCB manufacturing limitations, the weaving pattern is almost never aligned with each trace. Instead, the braid and the track will be arranged at an angle between them, and the angle will affect the skew by creating a phase delay. The lateral offset between the knitting pattern and the trace will also affect the skew.

In the time domain, this affects the propagation delay of the signal in a given trace. The skew in these cases is usually quantified in units of ps/inch. Longer traces will accumulate greater skew, and for medium-length traces, the skew can reach a few picoseconds. This greatly increases the possibility of signal degradation in devices operating at Gbps. High-speed laminates are often used to compensate for these signal degradation problems in multilayer PCBs.

3. Mismatched traces are on the PCB

In PCB design, timing offsets caused by mismatched length or propagation delay are usually compensated by zigzag traces. Signal nets with mismatched trace lengths can match all trace lengths to the longest trace in the network. The curve needs to be added to the shorter trace to increase its length.