PCB Technical - PCB design technology based on high-speed FPGA

If high-speed PCB design can be as simple as connecting schematic nodes and as beautiful as you can see on a computer monitor, it will be a wonderful thing. However, unless designers are new to PCB design, or are extremely lucky, actual PCB design is usually not as easy as the circuit design they are engaged in. Before the design can finally work normally and someone confirms the performance, PCB designers are faced with many new challenges. This is the current status of high-speed PCB design-design rules and design guidelines continue to evolve. If you are lucky, they will form a successful solution.

The vast majority of PCBs are schematic designers who are proficient in the working principle and mutual influence of PCB devices and various data transmission standards that constitute the input and output of the circuit board. The result of mutual cooperation between professional layout designers of what will happen after conversion to printed circuit copper wire. Usually, it is the schematic designer who is responsible for the success or failure of the final circuit board. However, the more a schematic designer knows about excellent layout techniques, the more opportunities there are to avoid major problems.

If the design contains high-density FPGAs, there are likely to be many challenges placed in front of the well-designed schematic. Including hundreds of input and output ports, operating frequencies over 500MHz (may be higher in some designs), and solder ball pitches as small as half a millimeter, all of which will cause undesirable interference between design units. Mutual influence.

Concurrent switching noise

In order to solve the ringing and crosstalk on high-speed data lines, switching to differential signals is a good first step. Since one line on the differential pair is the sink end and the other provides the source current, it can fundamentally eliminate the inductive effect. When using a differential pair to transmit data, because the current remains local, it helps to reduce the "bounce" noise generated by the induced current in the return path. For radio frequencies up to hundreds of MHz or even several GHz, signal theory shows that the maximum signal power can be transmitted when impedance is matched. When the transmission line is not well matched, reflections will occur, and only part of the signal will be transmitted from the sender to the receiving device, while other parts will bounce back and forth between the sender and the receiver. The quality of the differential signal implementation on the PCB will have a great effect on impedance matching (and other aspects).

Differential trace design

Differential trace design is based on the principle of PCB with controlled impedance. The model is a bit like a coaxial cable. On a PCB with controlled impedance, the metal plane layer can be used as a shielding layer, the insulator is an FR4 laminate, and the conductors are signal trace pairs (see Figure 1). The average dielectric constant of FR4 is between 4.2 and 4.5. Because the manufacturing error is not known, it may lead to over-etching of the copper wire, which will eventually cause impedance errors. The most accurate method to calculate the impedance of PCB traces is to use a field analysis program (usually two-dimensional, sometimes three-dimensional), which requires the use of finite elements to directly solve Maxwell's equations for the entire PCB in batches. The software can analyze EMI effects based on trace spacing, line width, line thickness, and the height of the insulating layer.

Decoupling and bypass capacitors

Another important aspect to determine whether the actual PCB performance meets expectations needs to be controlled by adding decoupling and bypass capacitors. Adding decoupling capacitors helps reduce the inductance between the PCB's power supply and the ground plane, and helps control the impedance of signals and ICs everywhere on the PCB. The bypass capacitor helps to provide a clean power supply for the FPGA (providing a charge bank). The traditional rule is that decoupling capacitors should be placed wherever PCB wiring is convenient, and the number of FPGA power pins determines the number of decoupling capacitors. However, the ultra-high switching speed of FPGA completely broke this stereotype.

In a typical FPGA board design, the capacitor closest to the power supply provides frequency compensation for load current changes. In order to provide low-frequency filtering and prevent the supply voltage from dropping, large decoupling capacitors are used. The voltage drop is due to a delay in the response of the voltage regulator when the design circuit is started. Such large capacitors are usually electrolytic capacitors with good low frequency response, and their frequency response ranges from DC to several hundred kHz.

Each FPGA output change requires charging and discharging the signal line, which requires energy. The function of the bypass capacitor is to provide local energy storage in a wide frequency range. In addition, a small capacitor with a small series inductance is needed to provide high-speed current for high-frequency transients. The large capacitor with slow response continues to provide current after the energy of the high-frequency capacitor is consumed.

In general, the wiring of the decoupling capacitor should be absolutely short, including the vertical distance in the via. Even a slight increase will increase the inductance of the wire, thereby reducing the effect of decoupling.

Other technologies

As signal speeds increase, it becomes increasingly difficult to easily transmit data on the circuit board. Some other techniques can be used to further improve the performance of the PCB.

The first and most obvious method is simple device layout. It’s common sense to design the shortest and most direct path for the most critical connections, but don’t underestimate this. Since the simplest strategy can get the best results, why bother to adjust the signal on the board?

An almost as simple method is to consider the width of the signal line. When the data rate is as high as 622MHz or higher, the skin effect of signal conduction becomes more prominent. When the distance is long, the very thin traces on the PCB (such as 4 or 5 mils) will form a great attenuation to the signal, just like a low-pass filter with no designed attenuation, its attenuation varies with The frequency increases and increases. The longer the backplane, the higher the frequency, and the wider the signal line should be. For backplane traces longer than 20 inches, the line width should reach 10 or 12 mils.

Usually, the most critical signal on the board is the clock signal. When the clock line is too long or poorly designed, it will amplify jitter and offset downstream, especially when the speed increases. You should avoid using multiple layers to transmit clocks, and don't have vias on the clock line, because vias will increase impedance changes and reflections. If the inner layer must be used to lay out the clock, the upper and lower layers should use ground planes to reduce the delay. When the design uses FPGA PLL, noise on the power plane will increase PLL jitter. If this is critical, you can create a "power island" for the PLL. This island can use a thicker etch in the metal plane to isolate the PLL analog power supply from the digital power supply.

Finally, and one of the best methods is to refer to the reference board provided by the FPGA manufacturer. Most manufacturers will provide the source layout information of the reference board, although special applications may be required due to private information issues. These circuit boards usually contain standard high-speed I/O interfaces because FPGA manufacturers need to use these interfaces when characterizing and certifying their devices. Keep in mind, however, that these circuit boards are usually designed for multiple purposes and may not exactly match specific design requirements. Even so, they can still be used as a starting point for creating solutions

Summary of this article

Of course, this article only talks about some basic concepts. Any of the topics covered here can be discussed in the length of the entire book. The key is to figure out what the goal is before investing a lot of time and effort in PCB layout design. Once the layout design is completed, the redesign will consume a lot of time and money, even if the width of the trace is slightly adjusted. You cannot rely on PCB layout engineers to make a design that can meet actual needs. The schematic designer must always provide guidance, make smart choices, and take responsibility for the success of the solution.