PCB Technical - How to make high-quality circuit boards faster with a good PCB layout

In order to obtain a better and faster PCB, designers need to pay attention to three main areas when designing circuit boards: building materials, component interconnection and wiring layout.

Building materials

In the PCB design process, designers mainly consider two main characteristics of PCB materials. One of them is the dielectric constant, and the other is the loss tangent. The dielectric constant affects the speed at which the signal passes through the circuit board. Loss tangent refers to the amount of signal lost due to absorption in the material. Although FR4 is a common material used to construct low-frequency circuits, more high-quality materials are still needed for those with frequencies exceeding 1 GHz.

Component interaction

For designers of high-frequency boards, it is very important to consider the connection points between the components and the PCB. The use of surface mount devices (SMD) has smaller structural features and lead lengths, so this problem can be solved to a large extent. However, as the frequency increases, passive components including SMD forms may have non-ideal characteristics. The designer must take this into consideration and compensate for these characteristics.

Trace layout

Once the designer has satisfactorily determined the choice of building materials and components, he/she must aim to achieve high-speed operation in a low-power environment. This involves:

.Minimize the generation of vehicle noise

.Minimize crosstalk between traces

.Reduce the impact of ground rebound

.Impedance matching

.Correct signal wire termination

Minimize noise generation

There are two main aspects to reducing noise. One of them is power distribution across the board, and the other involves power noise filtering.

In order to distribute power on the entire PCB, designers can use power planes or power bus networks. Generally, the power layer on a multilayer PCB consists of two or more metal layers that carry Vcc and GND to the device. Since the power plane covers almost the entire area of the PCB, the DC resistance of these planes is low. Therefore, the power plane keeps the Vcc level constant while evenly distributing the Vcc level to all devices. It also provides noise protection, extremely high current absorption capability and good shielding of the signals carried by the PCB.

An alternative to the power plane is the power bus, which consists of two or more wide metal traces that carry Vcc and GND to the device. Since this method is cheaper than power planes, two-layer PCBs often use them. When designing with a power bus network, the designer needs to ensure that the trace width is as wide as possible. However, compared with the power plane, the DC resistance of the power bus network is much lower.

Separating the plane and power bus that carry the analog and digital power supplies helps minimize the generation of airborne noise because it prevents the interaction between the two. However, an all-digital system may not have a separate analog power plane, and adding a new power plane may become very expensive unless the designer creates a partitioned island or separation plane on the existing layer.

Although it is recommended to separate these planes between the analog power and digital power on the system, there may still be some unnecessary interactions between the two circuit types.

Minimize the interaction between traces

Unnecessary coupling of signals between horizontal lines can cause crosstalk. Designers can minimize crosstalk through proper routing and the use of microstrip and stripline layouts in the layer stack.

When forced to use two signal layers next to each other, designers minimize crosstalk by routing all traces in one layer at an angle to the traces in the next layer. Other techniques they use to minimize crosstalk are to minimize the distance between the signal layer and its adjacent planes, and to increase the distance between two signal layers.

Reduce the impact of ground rebound

Using faster digital devices and reducing output switching time, the device output will show higher transient currents when the load capacitance is released. In addition, there may be multiple outputs of a device that switch from logic high to logic low at the same time. At the same time, pouring current into the ground may temporarily raise the ground potential, causing the baseline to change. This phenomenon is ground bounce. The main conditions that affect ground bounce include load capacitance, socket inductance and the number of simultaneous switching outputs.

Designers use the following design methods to reduce ground rebound:

.Place the vias near the capacitor pads, or use short and wide traces between them

. Use wide and short traces from power pins to power planes, islands or decoupling capacitors. This reduces the possibility of ground bounce by reducing the series inductance, and the transient voltage drops from the power supply pin to the power plane.

.Connect each ground pin or via to the ground plane. The daisy chain results in a shared ground path, which increases the resistance and inductance of the loop current loop

.Add decoupling capacitors as recommended by the IC manufacturer. The decoupling capacitor must be as close as possible to the power and ground pins of the device.

.Move the switch output as close to the ground pin of the package as possible

.Avoid pull-up resistors and use more pull-down resistors

.Use a multi-layer PCB with separate Vcc and GND planes to utilize the intrinsic capacitance of the Vcc-GND plane

.Use synchronous design, because these are not affected by synchronous switch pins

.The distance between the ground pin and the power pin is very close, thereby reducing the mutual inductance, because the current direction of the two pins is opposite.

.Minimize the inductance in the decoupling capacitor by using a larger via size on the capacitor pad

.Minimize lead inductance by using surface mount capacitors

.Use capacitors with lower effective series resistance

Impedance matching and correct signal line termination. Signals reflected back and forth along the mismatched impedance line will cause ringing at the load receiver. Ringing can cause false triggering of the receiver because it reduces the dynamic range of the receiver. Designers eliminate reflections by using proper signal line termination to make the source impedance equal to the trace impedance and load impedance.

In order to correctly match the impedance and terminate the signal line, the designer can ensure signal integrity through the following methods:

.Do not use vias in the clock transmission line, because vias will cause impedance changes and reflections

.Keep it straight. Do not use right-angle bends, but use curved trajectories

.Use point-to-point clock traces as much as possible, and terminate the clock signal to minimize reflections

.Use external equipment to buffer the load and limit the load capacitance

.Add a resistance of 10 to 27 ohms in series at each switch output to limit the current

.Place a suitable terminal resistance and ensure that the impedance matching between the transmission line and the terminal is equal to the line impedance

.Interlayer routing clock trace layer in the reference plane to minimize noise

.Keep the trace length below 5 cm, keep the impedance below 65 ohms, keep the metal delay below 940 ps, keep the inductance value below 40 nH, keep the trace capacitance below 20 pF, and The total capacitance is kept below 30 pF, especially for critical high-speed wiring.

in conclusion

In addition to choosing suitable high-frequency materials, designers can also use many better PCB layouts to make them work properly at high frequencies. Since each PCB is unique, it must be customized for its application. Using PCB CAD or design kit software can help designers because the software package provides a wide range of functions.