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PCBDesign Checking Point
1. Whether the information received in the process is complete (including: schematic diagram, *. BRD file, material sheet, PCB design description, PCB design or change requirements, standardization requirements, process design description)
2. Confirm that the PCB template is up to date
3. Confirm the correct position of the template positioning device
4.PCB design description, PCB design or change requirements, standardization requirements are clear
5. Confirm that the prohibited placement devices and wiring areas on the outline diagram have been shown on the PCB template
6. Compare the outline drawing, confirm the correct size and tolerance of the PCB, and the accurate definition of metallized and nonmetallic holes
7. After confirming the accuracy of PCB template, it is better to lock the structure file so as not to move the position by mistake
8. Confirm whether all device packages are consistent with the company unified library and whether the package library has been updated (check the running results with viewlog). If not, be sure to Update Symbols
9. Motherboard and motherboard, single board and backboard, confirm the signal correspondence, position correspondence, connector direction and silk screen identification are correct, and the motherboard has anti-misinsertion measures, the components on the motherboard and motherboard should not interfere
10. Whether the components are placed 100%
11. Open the place-bound of TOP and BOTTOM layers of the device and check whether DRC caused by overlap is allowed
12. Whether Mark point is sufficient and necessary
13. Heavy components should be placed near the PCB support point or support edge to reduce the warpage of the PCB
14. It is better to lock the structure-related devices after they are properly arranged to prevent misoperation and movement
15. Within 5mm around the crimping socket, no components higher than the height of the crimping socket shall be allowed on the front side, and no components or welding spots shall be allowed on the back side
16. Confirm whether the device layout meets the technological requirements (focus on BGA, PLCC and SMT socket)
17, metal shell components, especially pay attention to do not touch with other components, to leave enough space position
18. Interface related devices should be placed as close as possible to the interface, and the backplane bus driver should be placed as close as possible to the backplane connector
19. Whether the CHIP device on the wave soldering surface has been converted into the wave soldering package,
20. Whether there are more than 50 manual welding spots
21. Horizontal installation should be considered for high axial insertion of components on the PCB.Put apart lie put space.And consider the fixation mode, such as crystal oscillator fixed pad
22. Devices that need to use the heat sink must be spaced sufficiently from other devices and note the height of the main device within the heat sink range
23. Whether the digital circuit and analog circuit components of the digital-analog hybrid board have been separated and whether the signal flow is reasonable
24, A/D converter is placed across the modular partition.
25, whether the clock device layout is reasonable
26. Is the layout of high-speed signal device reasonable
27. Whether the end device has been properly placed (the source end matching serial resistance should be placed at the driver end of the signal;The matched string resistance in the middle is placed in the middle position;Terminal matching resistance should be placed at the receiving end of the signal)
28, whether the number and position of decoupling capacitance of IC device is reasonable
29. The signal line takes the plane of different levels as the reference plane. When crossing the plane segmentation area, whether the connection capacitance between the reference planes is close to the signal wiring area.
30. Whether the layout of the protection circuit is reasonable and conducive to segmentation
31. Is the fuse for the single board power supply placed near the connector and does not have any circuit elements in front of it
32, confirm the strong signal and weak signal (power difference of 30dB) circuit separate layout
33. Whether devices that may affect EMC experiments are placed according to design guidelines or successful experience.For example, the reset circuit of the panel should be a little closer to the reset button
34. Heat sensitive components (including liquid dielectric capacitance and crystal oscillator) should stay away from high-power components, radiator and other heat sources as far as possible
36. Whether the IC power source is too far away from IC
37. Whether LDO and surrounding circuit layout is reasonable
38. Whether the circuit layout around the module power supply is reasonable
39. Whether the overall layout of the power supply is reasonable
40, whether all simulation constraints have been correctly added to the Constraint Manager
41. Whether the physical and electrical rules are set correctly (note the constraint Settings of power network and ground network)
42. Whether the spacing Settings of Test Via and Test Pin are sufficient
43. Whether the thickness of the laminate and the scheme meet the design and processing requirements
44. Whether the impedance of all difference lines with characteristic impedance requirements has been calculated and controlled by rules
45. Whether the wiring of digital circuit and analog circuit has been separated and whether the signal flow is reasonable
46, A/D, D/A and similar circuits if the ground is divided, do the signal lines between the circuits go from the bridge junction between the two places (except the difference line)?
Signal lines that must cross the gap between split power sources shall refer to the complete ground plane.
48, if the stratigraphic design partition is not divided, to ensure that the digital signal and analog signal partition wiring.
49. Whether the impedance of high-speed signal line is consistent at each layer
50. Are high-speed differential signal lines and similar signal lines of equal length, symmetrical and parallel to each other?
Make sure the clock line goes as far as possible to the inner layer
52. Confirm whether the clock line, high-speed line, reset line and other strong radiation or sensitive lines have been wired according to the 3W principle as far as possible
53. Is there no biasing test point on clock, interrupt, reset signal, 100 / gigabit Ethernet, high-speed signal?
54. Whether LVDS and other low-level signals and TTL/CMOS signals meet the requirement of 10
H (H is the height of the signal line from the reference plane)?
55. Do clock lines and high-speed signal lines avoid passing through dense through-hole and through-hole areas or between device pins?
56, whether the clock line has met the requirements (SI constraint) (whether the clock signal routing should be less punched holes, short routing, continuous reference plane, the main reference plane should be GND as far as possible;If the GND main reference plane layer is changed during layer change, it is GND through the hole within the range of 200mil away from the hole) if the main reference plane of different levels is changed during layer change, is there decoupling capacitance within 200mil away from the hole?
57. Whether differential pairs, high-speed signal lines and all kinds of buses have met the requirements (SI constraint)
58. Is there a layer under the crystal oscillator?Is it possible to avoid signal line crossing between device pins?For high speed sensitive devices, is it possible to avoid signal line crossing between device pins?
59, veneer signal line can not have an acute Angle and right Angle (generally 135 degrees Angle continuous turn, rf signal line had better use circular arc or after calculation Angle cutting copper foil)
60. For dual panels, check whether the high-speed signal line is wired closely to its backflow ground line;For multilayer boards, check that the high-speed signal line is as close to the ground as possible
61, for the adjacent two layers of signal line, as far as possible vertical line
Avoid signal line crossing from power module, common mode inductor, transformer and filter
63. Try to avoid long distance parallel wiring of high-speed signals on the same layer
64. Are there any shielded holes on the edge of the plate with digital, analog and protective edges?Are multiple ground planes connected by holes?Is the hole distance less than 1/20 of the wavelength of the highest frequency signal?
65. Is the signal routing of the surge suppression device short and thick on the surface?
66. Confirm that there are no isolated islands, excessive grooves, long ground plane cracks caused by the over-large through-hole isolation plate or dense through-hole, no thin strips and narrow channels
67. Whether there is a ground pass hole (at least two ground planes are needed) in the place where the signal line crosses many layers.
68. If the power/ground plane is split, try to avoid high-speed signal crossing on the split reference plane.
Confirm that the power supply and ground can carry enough current.(estimation method: 1A/mm wire width at 1oz thickness of outer copper, 0.5a /mm wire width at inner layer, short-wire current doubled)
70. For the power supply with special requirements, whether it meets the requirements of voltage drop
71. In order to reduce the edge radiation effect of the plane, the 20H principle should be satisfied between the power layer and the stratum as far as possible.If possible, the power layer should be indented as much as possible.
If there is a partition, does the partition not constitute a loop?
73. Do different power planes of adjacent layers avoid overlapping?
Is the isolation of protected land, -48v land and GND greater than 2mm?
Is the 75, -48v site just a -48v signal backflow, not wired to another site?If not, please explain the reason in the remarks column.
76. Is a 10~20mm protective area to be covered near the connector panel and connected with each layer by double row of staggered holes?
77. Is the distance between the power line and other signal lines in accordance with safety regulations?
78. Under metal shell devices and heat dissipation devices, there shall be no wiring, copper sheet and hole passing that may cause short circuit
79. There shall be no wiring, copper, or through-hole around the mounting screw or washer that may cause a short circuit
80. Whether there is wiring in the reserved position in the design requirements
81. The inner layer separation line and copper foil spacing of non-metallic holes should be greater than 0.5mm (20mil), the outer layer 0.3mm (12mil), and the inner layer separation line and copper foil spacing of bearing hole of veneer drawing wrench should be greater than 2mm (80mil).
82, copper sheet and wire to plate edge is recommended to be greater than 2mm and minimum 0.5mm
83, inner layer copper sheet to plate edge 1 ~ 2 mm, minimum 0.5mm
84. For CHIP components (0805 and below) mounted on two pads, such as resistors and capacitors, the printed wire connected to the pad should be drawn symmetrically from the center of the pad and should have the same width as the printed wire connected to the pad. This provision may not be considered for the outgoing wire whose line width is less than 0.3mm(12mil)
85. A pad connected to a wider print line, preferably with a narrow print line in the middle.(0805 and below)
86, the line should be as far as possible from the SOIC, PLCC, QFP, SOT and other devices at both ends of the solder pad
K. screen printing
87. Whether the device bit number is missing and whether the position can correctly identify the device
88, whether the device bit number meets the company's standard requirements
89. Confirm the pin sequence of the device, the first pin mark, the polarity mark of the device and the correct direction mark of the connector
90. Whether the direction identification of the plug board of the mother board and the child board corresponds to each other
91. Whether the back plate correctly identifies the slot name, slot number, port name and sheath direction
92. Confirm whether the silk screen required by the design is added correctly
93. Confirm that anti-static and rf plate identification (for rf plate) have been placed.
Confirm PCB code is correct and conform to company specification
95. Confirm that the PCB coding position and layer of the single board are correct (it should be on the top left of side A, screen printing layer).
96. Confirm that the PCB coding position and layer of the back plate are correct (it should be in the upper right part of B, the outer copper foil surface).
Confirm bar code laser printing white silk screen marking area
98, confirm that there is no connection line below the bar code box and that the hole is larger than 0.5mm
99, confirm the bar code white screen printing area outside the 20mm range cannot have the height of more than 25mm components
100, in the reflow surface, through hole can not be designed on the pad.(the spacing between the hole and the pad with normal window opening should be greater than 0.5mm (20mil), and the spacing between the hole and the pad covered by green oil should be greater than 0.1mm (4mil).
101, the arrangement of the holes should not be too close, to avoid causing a wide range of power supply, ground plane fracture
102. The hole diameter of the drilling hole should not be less than 1/10 of the thickness of the plate
103, whether the device placement rate is 100%, whether the device placement rate is 100% (if the device placement rate is not 100%, please refer to the note)
104, whether the Dangling line has been adjusted to the minimum, and the retained Dangling line has been confirmed one by one.
Whether the process problems fed back by the technology section have been carefully checked
106. For large areas of copper foil on Top and bottom, if there is no special need, apply mesh copper [inclined net for veneer, orthogonal net for back plate, line width 0.3mm (12 mil), spacing 0.5mm (20mil)]
107, large area of copper foil area component pad, should be designed into a flowered pad, so as to avoid virtual welding;When the current requirements, the first consideration of the reinforcement of the plate, and then consider the full connection
108, large area of copper cloth, should try to avoid the appearance of no network connection dead copper (island)
109, large area copper foil also need to pay attention to whether there is illegal wiring, unreported DRC
110. Whether the test points of various power sources and ground are sufficient (at least one test point for every 2A current)
Verify that networks without test points are validated for streamlining
112, verify that test points are not set on plug-ins that are not installed at production time
113. Have Test Via and Test Pin been fixed (applicable to the unchanged change plate of Test needle bed)
The Spacing Rule of Test via and Test pin should be set to the recommended distance first check DRC if DRC is still present then check DRC with the minimum distance setting
115, open constraint set to open state, update DRC, check if there are any unallowed errors in DRC
116, confirm that DRC has been adjusted to a minimum and that DRC cannot be eliminated.
Confirm that there is an optical positioning symbol on the PCB surface with mounting components
118, confirm that the optical positioning symbol is not pressed (silk screen printing and copper foil wiring)
119. The background of the optical registration point should be the same. Confirm that the center of the optical point of the whole plate is ≥5mm away from the edge
120. Confirm that the optical positioning reference symbol of the whole plate has been assigned a coordinate value (it is recommended that the optical positioning reference symbol be placed as a device) and that the integer value is in millimeter.
121. For IC devices with center distance between pins<0.5mm and BGA devices with center distance < 0.8mm (31 mil), optical registration points shall be set near the diagonal of components
122, confirm whether there are special requirements for the type of solder pads are correctly opened Windows (especially pay attention to the hardware design requirements)
123. Whether the through hole under BGA is treated as the cover oil plug hole
124, whether the hole other than the tested hole has been made small window or cover oil plug hole
125. Whether the opening of the optical registration point avoids exposed copper and exposed line
126. Whether the power chip, crystal oscillator and other devices that need copper skin to dissipate heat or earth shield have copper skin and open the window correctly.The device fixed by solder shall have green oil to block the large area of solder diffusion
127, Notes PCB board thickness, number of layers, screen printing color, warp, and other technical specifications are correct
128. Whether the layer name, stack sequence, medium thickness and copper foil thickness of the stack diagram are correct;Whether impedance control is required and whether the description is accurate.Whether the layer name of the laminate is the same as the light drawing file name
129. Close the Repeat code in the setting table and set the drilling accuracy to 2-5
130, are the hole table and hole file up to date (must be regenerated when holes are changed)
131, whether there is an abnormal aperture in the hole table, whether the aperture of the compression piece is correct;Whether the aperture tolerance is marked correctly
132. Is the hole through the fortress hole listed separately and marked with "filled vias"?
133, light drawing file output as far as possible RS274X format, and the accuracy should be set as 5:5
134, whether art_aper.txt is the latest (274X is not needed)
135, output light draw file log file whether there is an exception report
136, negative layer edge and island confirmation
137. Use the light drawing inspection tool to check whether the light drawing file is consistent with PCB (use the alignment tool to compare the board).
138, PCB file: product model _ specification _ single board code _ version number. BRD
139, backing board design document: product model _ specification _ single board code _ version no. -cb [-t /B]. BRD
140, PCB processing file: PCB coding. Zip (including light drawing file, aperture table, drilling file and ncdrp.log of each layer;The jigsaw board also needs the jigsaw board file provided by the process *.dxf), and the backing board also needs the backing board file: PCB code-cb [-t /B]. Zip (including drill. Ar)
141, process design document: product model _ specification _ single board code _ version number - gy. doc
142, SMT coordinate file: product model _ specification _ single board code _ version number - smt.txt, (when output coordinate file, confirm to select Body center, only when confirm that the origin of all SMD device library is the device center, can select Symbol origin)
143, PCB board structure file: product model _ specification _ single board code _ version number - McAd.zip (including.DXF and.EMN files provided by the structural engineer)
144, TEST file: product model _ specification _ single board code _ version number - test.zip (contains testprep. Log and untest.lst or *.drl TEST point coordinate file)
PDF, (including cover, home page, each layer screen printing, each layer line, borehole drawing, back plate including backing plate drawing)
146, confirm the information of cover and front page is correct
147. Confirm that the drawing serial number (corresponding to the sequence distribution of PCB layers) is correct
148, confirm that the PCB code on the drawing frame is correct
