PCB Technical - Signal Integrity Design of Gigabit Equipment PCB

This article mainly discusses the signal integrity design issues that need to be considered in gigabit data transmission, and at the same time introduces the use of PCB design tools to solve these problems, such as skin effect and dielectric loss, the influence of vias and connectors, differential signals and Wiring considerations, power distribution and EMI control, etc.

The rapid development of communication and computer technology has made high-speed PCB design enter the gigabit field. The application of new high-speed devices makes it possible to transmit such high speeds over long distances on the backplane and single board. At the same time, PCB design The signal integrity issues (SI), power integrity and electromagnetic compatibility issues are also more prominent. Signal integrity refers to the quality of the signal transmitted on the signal line. The main problems include reflection, oscillation, timing, ground bounce, and crosstalk. Poor signal integrity is not caused by a single factor, but a combination of multiple factors in board-level design. In the PCB board design of gigabit equipment, a good signal integrity design requires engineers to fully consider the issues of components, transmission line interconnection schemes, power distribution and EMC. High-speed PCB design EDA tools have evolved from pure simulation verification to a combination of design and verification, helping designers set rules early in the design to avoid errors instead of finding problems later in the design. As the data rate becomes higher and the design becomes more and more complex, high-speed PCB system analysis tools become more necessary. These tools include timing analysis, signal integrity analysis, design space parameter scan analysis, EMC design, power system stability analysis, etc. . Here we will focus on some issues that should be considered in signal integrity analysis in the PCB design of gigabit devices.

High-speed devices and device models

Although the Gigabit transmitting and receiving component suppliers will provide design information about the chip, there is also a process for the component supplier to understand the signal integrity of the new device, so the design guidelines given by the component supplier may not be mature. Yes, the design constraints given by the device supplier are usually very harsh, and it is very difficult for the design engineer to meet all the design rules. Therefore, it is necessary for signal integrity engineers to use simulation analysis tools to analyze the supplier’s constraint rules and actual design, investigate and optimize component selection, topology, matching scheme, and value of matching components, and finally develop to ensure signal integrity PCB layout and routing rules. Therefore, accurate simulation analysis of gigabit signals has become very important, and the role of device models in signal integrity analysis has also been paid more and more attention.

The component model usually includes an IBIS model and a Spice model. Because board-level simulation only cares about the signal response from output pins to input pins through the interconnection system, and IC manufacturers do not want to leak detailed circuit information inside the device, and the simulation time of the transistor-level Spice model is usually unbearable, so the IBIS model is used in high-speed PCBs. The design field is gradually accepted by more and more device manufacturers and signal integrity engineers.

For the simulation of gigabit equipment PCB systems, engineers often question the accuracy of the IBIS model. When the device works in the saturation and cut-off region of the transistor, the IBIS model lacks sufficient detailed information to describe it. In the non-linear region of the transient response, the simulation results with the IBIS model cannot produce accurate response information like the transistor-level model. However, for ECL type devices, an IBIS model that is very consistent with the simulation results of the transistor-level model can be obtained. The reason is simple. The ECL driver works in the linear region of the transistor, and the output waveform is closer to the ideal waveform. According to the IBIS standard, it can be more accurate. IBIS model.

As the data transmission rate increases, differential devices developed on the basis of ECL technology have been greatly developed. LVDS standards and CML etc. make it possible to transmit gigabit signals. It can be seen from the above discussion that the IBIS standard is still suitable for the design of gigabit systems due to the circuit structure and the corresponding differential technology application. Some published application articles of IBIS model in 2.5GbpsLVDS and CML design also prove this point.

Since the IBIS model is not suitable for describing active circuits, for many Gbps devices with pre-emphasis circuits for loss compensation, the IBIS model is not suitable. Therefore, in the design of a gigabit system, the IBIS model can only work effectively under the following conditions:

1. Differential devices work in the amplification area (linear V-I curve)

2. The device has no active pre-emphasis circuit

3. The device has a pre-emphasis circuit but does not start (activating the pre-emphasis function in a short interconnected system may lead to worse results)

4. The device has a passive pre-emphasis circuit, but the circuit can be separated from the die of the device.

When the data rate is 10Gbps or above, the output waveform is more like a sine wave, and then the Spice model is more applicable.

Loss effect

When the signal frequency increases, the attenuation on the transmission line cannot be ignored. At this time, it is necessary to consider the loss caused by the equivalent resistance of the conductor in series and the equivalent conductance of the medium in parallel, and the lossy transmission line model needs to be used for analysis.

The equivalent model of a lossy transmission line is shown in Figure 1. It can be seen from the figure that the equivalent series resistance R and the equivalent parallel conductance G are characterizing the loss. The equivalent series resistance R is the resistance caused by the DC resistance and the skin effect. The DC resistance is the resistance of the conductor itself, which is determined by the physical structure of the conductor and the resistivity of the conductor. When the frequency increases, the skin effect starts to work. The skin effect is a phenomenon in which the signal current in the conductor concentrates on the surface of the conductor when a high-frequency signal passes through the conductor. Inside the conductor, the signal current density decays exponentially along the cross-section of the conductor, and the depth at which the current density decreases to the original 1/e is called the skin depth. The higher the frequency, the smaller the skin depth, resulting in an increase in the resistance of the conductor. The skin depth is inversely proportional to the square root of the frequency.

The equivalent parallel conductance G is also called dielectric loss (DielectricLoss). At low frequencies, the equivalent parallel conductance is related to the bulk conductivity and equivalent capacitance of the medium, and when the frequency increases, the dielectric loss angle begins to play a leading role. At this time, the dielectric conductivity is determined by the dielectric loss angle and the signal frequency.

Generally speaking, when the frequency is less than 1GHz, the skin effect loss plays a major role, and when the frequency is above 1GHz, the dielectric loss dominates.

In the simulation software, you can set the dielectric constant, dielectric loss angle, conductor conductivity, and cut-off frequency. The software will consider the skin effect and dielectric loss according to the structure of the transmission line during simulation. If attenuation is simulated, the corresponding cutoff frequency must be set according to the bandwidth of the signal. The bandwidth is determined by the signal edge rate. The edge rate of many 622MHz signals and 2.5GHz signals is not much different. In addition, the equivalent can be seen in the model of lossy transmission lines. Resistance and conductance vary with frequency.

It can be seen from Figure 2 that loss slows the rising edge of the signal, that is, reduces the bandwidth of the signal, and loss reduces the amplitude of the signal. On the other hand, this is good for suppressing signal overshoot.

The crosstalk of the transmission line also affects the loss. Crosstalk is determined by the physical structure of the transmission line, coupling length, signal strength and edge rate. After a certain length, the crosstalk will saturate, but the loss will not necessarily increase.

Influence of vias and connectors

Vias transmit the signal to the other side of the board. The vertical metal part between the boards is uncontrollable impedance, and the inflection point from horizontal to vertical is a breakpoint, which will cause reflection, so its appearance should be minimized (Figure 3).

In the design and simulation of a gigabit system, the influence of vias must be considered, and a via model is required. The model structure of the via is in the form of a series resistance R, an inductance L and a parallel capacitance C. According to specific applications and accuracy requirements, multiple RLC structures can be used in parallel, and coupling with other conductors can be considered. At this time, the via model is a matrix.

There are two methods for obtaining the via model. One is to obtain it through testing, such as TDR, and the other can be extracted by a 3D field extractor (FieldSolver) based on the physical structure of the via.

Via model parameters are related to the material, stack, thickness, pad/anti-pad size of the PCB, and the connection method of the wire connected to it. In the simulation software, different parameters can be set according to the accuracy requirements. The software will extract the model of the via according to the corresponding algorithm and consider its influence during the simulation.

In the design of the gigabit system PCB, the influence of the connector should be especially considered. The development of high-speed connector technology can already guarantee the continuity of the impedance and the ground plane during signal transmission. The simulation analysis of the connector in the design is mainly Use a multi-line model.

The connector multi-line model is a model extracted in a three-dimensional space considering the inductance and capacitance coupling between the pins. The connector multi-line model generally uses a three-dimensional field extractor to extract the RLGC matrix, which is generally in the form of a Spice model sub-circuit. Due to the complex structure of the model, it takes a long time for extraction and simulation analysis. In SpecctraQuest software, you can edit the Spice model of the connector into an Espice model, assign it to the device or call it directly, or edit it into a package model in DML format and assign it to the device.

Differential signal and wiring considerations

Differential signal has the advantages of strong anti-interference and high transmission rate. In gigabit signal transmission, it can better reduce the influence of crosstalk and EMI. Its coupling forms include edge coupling and upper and lower coupling, loose coupling and tight coupling.

Compared with the upper and lower coupling, the edge coupling has the advantages of better reduction of crosstalk, convenient wiring, simple processing, etc., and the upper and lower coupling are more often applied to PCB boards with high wiring density. Compared with loose coupling, tight coupling has better anti-interference ability and can reduce crosstalk, while loose coupling can better control the continuity of differential trace impedance.

Specific differential routing rules should consider the impact of impedance continuity, loss, crosstalk, and trace length differences according to different situations. It is best to use eye diagrams to analyze simulation results for differential lines. The simulation software can set the random sequence code to generate the eye diagram, and can input the jitter and offset parameters to analyze its impact on the eye diagram.

Power distribution and EMC

The increase in data transmission rate is accompanied by a faster edge rate, and it is necessary to ensure power supply stability in a wider frequency band. A high-speed system may pass a transient 10A current and requires a maximum power supply ripple of 50mV, which means that the impedance of the power distribution network within a certain frequency range must be within 5mΩ. For example, the rise time of the signal is less than 0.5ns. The bandwidth range is up to 1.0GHz.

In the design of a gigabit system, it is necessary to avoid the interference of synchronous noise (SSN) and ensure that the power distribution system has a lower impedance within the bandwidth. Generally, in the low frequency band, decoupling capacitors are used to reduce the impedance, and in the high frequency band, power supply and ground plane distribution are mainly considered. Figure 4 shows the frequency response diagram of impedance changes when decoupling capacitors are considered for power and ground plane layers and when the decoupling capacitors are not considered.

SpecctraQuest software can analyze the impact of synchronous noise caused by the package structure. The PowerIntegrity (PI) software uses frequency domain analysis of the power distribution system, which can effectively analyze the number and location of decoupling capacitors and the effects of power and ground planes, helping engineers Carry out decoupling capacitor selection and placement, wiring and plane distribution analysis.