PCB Technical - Signal integrity analysis of MCM high-speed circuit layout design

Abstract: With the increase of packaging density and the increase of operating frequency, the signal integrity problem in MCM circuit design cannot be ignored. This article takes the detector circuit as an example. First, the layout design of the circuit is realized by using APD software, and then combined with the signal integrity analysis, the circuit layout structure is repeatedly adjusted. The final Spectra Quest software simulation results show that the improved circuit layout Meet the signal integrity requirements while maintaining high simulation accuracy.

Keywords: multi-chip components; place and route; signal integrity; reflection; delay

With the development of integrated circuit technology, the working speed of multi-chip components is getting higher and higher, and the processing of high-speed signals has become the key to the success of MCM circuit design. When the rising or falling edge of the clock signal is very small, it will cause transmission line effects, that is, signal integrity problems.

This design takes the detector circuit as an example, and elaborates on the method of MCM layout design using signal integrity analysis tools. First, expand the packaged parts library to meet the needs of specific circuit layout design; then use APD (Advanced Package Designer) software to directly call the component packaging symbols to complete the preliminary layout design of the circuit; finally combine reflection, delay and electromagnetic compatibility After the signal integrity simulation analysis results are repeatedly adjusted, the improved circuit layout reduces the reflection of the signal, the relative delay of the input signal does not exceed 0.2ns, and the electromagnetic interference phenomenon is also suppressed to meet the signal integrity requirements.

Software Realization of MCM Place and Route

As mentioned above, the realization of MCM layout includes the generation of circuit schematic diagrams, the expansion of the parts library and the final layout and routing completion and processing data file output. APD Layout includes five types: Padstack (*.pad), Package Symbol (*.psm), Mechanical Symbol (*.bsm), Format Symbol (*.osm) and Shape Symbol (*.ssm). In MCM layout design, All layouts must have the correct Library Packing. The built-in package library of MCM design software often cannot meet the specific design requirements. Only after the parts library is expanded, can the parts be directly used for layout design and final process file output. First, use Padstack Editor software to expand the part library, then package the circuit, and export the electrical connection netlist file to the APD software through Concept HDL, and finally complete the circuit layout. In the entire design, 16 Padstacks and 81 package symbols are defined, Padstack is called 251 times and functional units are called 89 times, among which 251 component package symbol pins and 229 functional unit pins are shared.

It should be noted that in the specific design, if Orcad is used for the preliminary circuit design, the file generated by Orcad must be converted into the mcm file of the APD software. But because the converted mcm file has a problem similar to brd, the Concept HDL software is used to export the netlist file, and then the network cable topology is extracted for simulation. In order to reduce the simulation time, a sub-module simulation method is adopted.

Simulation analysis

IBIS model

Spectra Quest is the same as other circuit analysis software. To obtain accurate simulation results, you must first provide accurate electrical models for circuit components. Spectra Quest software uses the IBIS model. The IBIS (Input/Output Buffer Information Specification) model uses I/V and V/T tables to describe the characteristics of I/O units and pins. It is a fast and accurate I/O buffer based on the V/I curve. The method of the model. It provides a standard file format to record parameters such as driver or receiver output impedance, rise/fall time and input load. These parameters are read by Spectra Quest. The IBIS model has the information needed for signal integrity analysis, and is very suitable for calculation and simulation of high-frequency effects such as oscillation and crosstalk.

The Sigxplorer inside Spectra Quest accepts the IBIS model, and then converts it into a unique design modeling language DML to complete the modeling of the complex I/O structure. Moreover, the Constraint Manager in Sigxplorer can manage the parameters used in the simulation and embed them in the subsequent placement and routing constraints.

Reflection analysis

The reflection, the echo on the transmission line, is caused by the discontinuity of impedance. The impedance mismatch between the source and the load will cause reflections on the line, and the load will reflect part of the voltage back to the source. If the load impedance is less than the source impedance, the reflected voltage is negative; otherwise, the reflected voltage is positive. The ideal situation is that the output impedance, transmission line impedance, and load impedance are all equal. At this time, the impedance of the transmission line is continuous and no reflection occurs. The amplitude of the reflected voltage signal is determined by the source reflection coefficient rS and the load reflection coefficient rL.

The key to solving transmission line reflection is impedance control. Impedance matching can suppress transmission line reflection. There are four matching termination methods: parallel termination, Thevenin equivalent parallel termination, AC termination and series termination. Here, the Thevenin equivalent parallel termination method is used to control the input impedance of the detector circuit, and then the circuit topology is extracted, and the transmission characteristics of the circuit before and after the matching termination are simulated respectively.

Before termination, the waveform is distorted on the rising edge, which is easy to cause misoperation. The matching termination effectively eliminates the distortion of the signal, and the monotonicity is very good, and the original signal is pulled up at the rising edge, and the level switching is entered in advance, which increases the steady-state time of the signal, and the rising edge of the signal is relatively stable. Although there is an overshoot in the high-level maintenance phase, it has no effect on signal confirmation, and the signal quality is ideal. In addition, the length of the signal transmission line also has a certain effect on reflection. The simulation found that when the transmission line was long, the predicted reflection phenomenon appeared; when the transmission line was short, the simulation waveform and the analysis result were in good agreement. Therefore, the wiring length is different, and its processing method should be different. Generally speaking, if the trace length is less than 2 inches, it is treated as a lumped parameter LC circuit; if it is greater than 8 inches, it is treated as a distributed parameter transmission line circuit.

Delay analysis

With the increase of the operating frequency of the system, when the signal rising or falling edge is very steep, the wiring delay can no longer be ignored. It plays a vital role in the establishment and maintenance of the signal, and may even affect the timing of the system and cause misoperation, so it must be considered. The MCM high-speed circuit design requires that the phase deviation of the memory chip cannot be too large, so the wiring delay from the driving end to the receiving end should be roughly equal. The length of the signal line has a great influence on the transmission quality, and may cause the signal to be distorted during the transmission process. The signal transmission quality becomes worse as the line length increases. For too long signal lines, the source or terminal matching method should be used to improve the transmission quality. Using signal integrity simulation tools, you can easily simulate the delay from the drive end to each chip, and then adjust the layout and routing according to the simulation results to meet the predetermined requirements.

Each signal of the detector should maintain the same transmission delay as much as possible, which requires the wiring to be as consistent in length as possible. For slight differences, the wiring can be extended or shortened according to the simulation results. After completing the wiring, use Spectra Quest software to simulate the transmission delay of the input signal. The specific parameters are shown in Table 2. It can be seen that the relative delay does not exceed 0.2ns, and the simulation result is ideal.

EMI analysis

The above analysis of signal reflection and delay in the time domain, in addition, EMI (electromagnetic interference) is also an important aspect of high-speed circuit design.

Electromagnetic interference includes excessive electromagnetic radiation and sensitivity to electromagnetic radiation. Too high operating frequency, too fast signal changes, or unreasonable layout and wiring can all cause electromagnetic interference effects. EMI simulations were performed on the detector circuits before and after the terminal matching by changing the wiring strategy. The noise generated by the signal continues from 0 to 2GHz, with a wide range, and the radiation intensity of each frequency is not the same. The radiation intensity of some frequencies exceeds the limit, that is, the electromagnetic interference of the signal at this frequency has exceeded the system's ability to withstand To the extent of this, measures should be taken to reduce its radiation level. Perform impedance control according to the aforementioned method and minimize the wiring length. It can be seen that the frequency wave exceeding the limit has dropped below the horizontal line, and the radiation intensity of each frequency point has been reduced, and the entire radiation intensity has been reduced. This shows that for signal transmission, changing the wiring length and adding an appropriate matching termination network not only improves the transmission characteristics of the signal, but also reduces the electromagnetic radiation intensity and improves the quality of the signal.

Concluding remarks

When designing high-speed circuits, first use accurate device models to perform signal integrity and EMI simulation analysis of system functions to determine the layout of the circuit, and then simulate to improve the wiring network until a satisfactory wiring result is obtained. This design mainly simulates and analyzes the reflection, delay and EMI problems of MCM placement and routing in the time domain and frequency domain based on the MCM layout design technology, combined with the detector packaging examples, and achieved good results.