PCB Blog - Fast steering and high quality of ate load board

"ate load board" was a term used in the semiconductor industry several years ago for automatic test equipment (ATE) PCBs. However, in recent years, they have been referred to as "device interface boards (DIBs)" or "processor interface boards (HIBs)" in the semiconductor industry. Chip manufacturers require rapid turnaround and high-quality evaluation of their newly produced and highly advanced products when ordering test boards, regardless of brand. This exceeds the requirements of previous generations of test boards. This is because chips are being manufactured much faster than they were a few years ago. Chip manufacturers are keen to test their products as soon as possible because they are producing them at a faster rate. The manufacturing time frame used to be two to three months, but today they are close to six to eight weeks. Chip manufacturers are demanding that their new chips be tested using ate load board as soon as possible, and they do not want millions of dollars worth of chips to sit idle.

ate load board

ATE PCB suppliers have two to three months to deliver these test boards. However, they now have six to eight weeks to complete the ATE PCB required by chip manufacturers. ATE PCB suppliers may increase their quotations by including other services. For example, when electronic manufacturing service (EMS) providers such as Naprotek provide wafer testing and inspection, processing, cutting, and semiconductor packaging in addition to ATM test boards, chip manufacturers receive rewards. In order to provide high-quality ATE PCBs, design knowledge and intelligent design methods are required. This includes a fine touch and accurate understanding of the layout and wiring related to the design of these large PCB board, as well as an understanding of all the subtle differences related to reducing ball grid array (BGA) packaging, significantly reducing the spacing between BGA balls, and a fine touch and accurate understanding of the layout and wiring related to the design of these large circuit boards.

Quality and accuracy

A well-designed and accurate ATE PCB is the result of various design methods, policies, and procedures. For example, the placement of bypass capacitors and the presence of voltage limitations must be ensured. As designers are now building 30 to 50 ply boards, there are other boards that go far beyond connecting to standard multilayer boards. High quality ATE test boards are created through a dedicated design process and adhere to strict manufacturing standards. Otherwise, the accuracy of the test board results will be affected. For example, the one with a high failure rate may not be accurate. When you do this, you will throw away decent chips and a lot of money. Therefore, this is where quality comes into play. The following are some preliminary steps taken by experienced ATE PCB designers to ensure quality and accuracy. First, they must evaluate the fact that BGA is heavily loaded in ATE PCBs today. As the packaging size of such devices continues to shrink, this packaging technology has become vibrant. Not only is BGA shrinking, but the pin spacing between BGA balls is also shrinking. Five years ago, the BGA spacing was 1.0 or 0.8 millimeters (mm). Today, it is between 0.25 and 0.3 millimeters. The significant reduction in pin spacing translates into challenging design constraints during PCB layout. Therefore, tighter spacing and smaller BGA are an aspect that experienced ate pcb design must consider. Also consider making the wiring width narrower. Two to three years ago, the wiring width was seven to eight mils. Today, they have shrunk to three to four mils.

Given these technological advances, ATE PCB designers must have sufficient experience to determine the correct layout and wiring. For example, designers are using a 0.3mm spacing BGA, which cannot fan out wiring with very wide routing. Instead, you must use a 3 to 4 mil routing. The previous technology was that when wiring was led out from BGA, they would be led out with different widths. After the wiring comes out, the designer will increase the width. But take today's BGA production of 25 or 3 million traces as an example. The designer was unable to significantly increase the trace to seven or eight mils. The result will be a significant signal loss or a change in speed or impedance based on the width of the change. Therefore, savvy designers need to take this into account when routing and selecting differential pair widths or high-speed routing. Differential pairs require a specific stack. These differential pairs are designed according to the requirements of the chip manufacturer. When manufacturing ATE boards, the manufacturing workshop needs to ensure that differential pairs are correctly impedance matched, and that the tolerance for these differential pairs is 5%. For example, if the differential pair matches a 100 ohm (Ω) impedance, the designer allows a tolerance of 5%, which means that the tolerance will be between 95 and 105 Ω. If the differential pair is not correctly matched according to the impedance provided to the manufacturer by the ate pcb design, the chip test results will not meet the required accuracy.