PCB News - Blind spots that PCB circuit design must know

Blind spot 1: Automatic distribution of thin lines for boards with low design requirements

Automatic routing will inevitably take up a larger PCB area, and at the same time produce many times the number of vias than manual routing. In a large batch of products, the factors that PCB manufacturers consider for price reduction are the line width and the number of vias, in addition to business factors., They respectively affect the yield of PCB and the number of consumption of drill bits, save the cost of the supplier, and find a reason for the price reduction.

Blind spot 2: All bus signals are pulled by resistors

There are many reasons why signals need to be pulled up and down, but not all of them need to be pulled. The pull-up and pull-down resistors pull a simple input signal, and the current is less than tens of microamperes, but when a driven signal is pulled, the current will reach the milliamp level. The current system often has 32 bits of address data each, and there may be If the 244/245 isolated bus and other signals are pulled up, a few watts of power consumption will be consumed on these resistors.

Blind spot 3: These unused I/O ports of CPU and FPGA leave it empty first

If the unused I/O port is left floating, it may become an input signal that oscillates repeatedly due to a little interference from the outside world, and the power consumption of the MOS device basically depends on the number of flips of the gate circuit. If it is pulled up, each pin will also have microampere current, so the best way is to set it as output (of course, no other signals with driving can be connected to the outside)

Blind spot 4: FPGA has so many doors left to use, so you can play to your heart’s content

The power consumption of FGPA is proportional to the number of flip-flops used and the number of flips. Therefore, the power consumption of the same type of FPGA at different circuits and different times may differ by 100 times. Minimizing the number of flip-flops for high-speed flipping is the fundamental way to reduce FPGA power consumption.

Blind spot five: the power consumption of small chips is very low, don't need to consider

It is difficult to determine the power consumption of the internally less complicated chip. It is mainly determined by the current on the pin. An ABT16244 consumes less than 1 mA without load, but its indicator is that each pin can be driven. A load of 60 milliamperes (such as matching a resistance of tens of ohms), that is, the maximum power consumption of a full load can reach 60*16=960mA. Of course, only the power supply current is so large, and the heat falls on the load.

Blind spot 6: The memory has multiple control signals. The board only needs to use the OE and WE signals, and the chip select is grounded, so that the data comes out much faster during the read operation

The power consumption of most memories when the chip selection is valid (regardless of OE and WE) will be more than 100 times larger than when the chip selection is invalid, so CS should be used to control the chip as much as possible, and as short as possible when other requirements are met. The width of the chip select pulse.

Blind spot seven: signal overshoot can be eliminated as long as it matches well

Except for a few specific signals (such as 100BASE-T, CML), there are overshoots. As long as they are not very large, they do not necessarily need to be matched. Even if they are matched, they do not necessarily match the best. For example, the output impedance of TTL is less than 50 ohms, and some even 20 ohms. If such a large matching resistance is used, the current will be very large, the power consumption will be unacceptable, and the signal amplitude will be too small to be used. Besides, the output impedance of a general signal when outputting a high level and outputting a low level is not the same, and there is no way to achieve a complete match. Therefore, the matching of TTL, LVDS, 422 and other signals can be acceptable as long as the overshoot is achieved.

Blind spot 8: Reducing power consumption is the job of hardware personnel, and has nothing to do with PCB design software

The hardware is just a stage, but the software is the performer. The access of almost every chip on the bus and the flip of every signal are almost controlled by the software. If the software can reduce the number of accesses to the external memory, respond to interrupts and other conflicts in a timely manner Specific measures for specific boards will make a great contribution to reducing power consumption.