PCB News - DDR PCB Layout rules

DDR PCB board Layout rules

In the wiring of ordinary printed PCB circuit boards, since the signal is a low-speed signal, it is generally connected according to the flow direction of the signal under the basic wiring rule of the 3W principle, and there is generally no problem. But if the signal is above 100M, the wiring is very particular. Since DDR signals with speeds up to 300M have been deployed recently, I will explain the wiring principles and techniques of DDR signals in detail.

High-speed systems generally use low-voltage signals, which have low voltage and small swing, which is easy to increase speed and reduce power consumption. Minimize internal resistance, such as using electrical planes, punching more holes, shortening the wiring distance, and using resistors to divide signals at the end of high voltage transmission to produce lower voltage signals. The signal voltages of SDRAM, DDR-I, DDR-II, and DDR-III are lower than one, making it increasingly difficult to stabilize. Also pay attention to the power supply, if the energy supply is insufficient, the memory will not work stably. The concept of signal integrity and transmission line is a relatively professional system knowledge, and it will not be described in detail here. Now, even if you don’t understand the concept of signal integrity and transmission lines, please follow the general basic rules below. The DDR high-speed signal board that is deployed will not cause problems.

1) DDR and the main control chip are as close as possible. All differential signal pairs in DDR high-speed signals must be strictly equal in length (up to 50 mils of redundancy is allowed), and the length of all signal lines and clock lines should not exceed 2500 mils. Try to 0 vias. There must be a well-grounded ground layer under the component layer, and all traces cannot cross the ground dividing slot, that is, the ground dividing line that crosses the signal line cannot be seen from the component layer through the ground layer. In this case, 400M DDR is basically no problem. Some other 3W, 20H rules can be done as much as possible.

2) Address and command signal group: maintain a complete ground and power plane. The characteristic impedance is controlled at 50～60 Ω. Keep the distance between the signal group and other non-DDR signals at least 20 mil. The signal in the group should match the length of the DDR clock line, and the gap should be at least within 500 mil. The value of the series matching resistance RS is 0～33 Ω, and the value of the parallel matching resistance RT should be 25～68 Ω. The signals in this group should not be in the same resistor row as the data signal group.

3) Control signal group: The control signal group has the least signals, with only two signals, clock enable and chip select. Still need to have a complete ground plane and power plane for reference. The value of the series matching resistance RS is 0～33 Ω, and the value of the parallel matching terminal resistance RT is 25～68 Ω. In order to prevent crosstalk, the signals in this group cannot be in the same resistor row as the data signals.

4) Data signal group: Take the ground plane as a reference to provide a complete ground plane for the signal loop. The characteristic impedance is controlled at 50～60 Ω. The line width can be the same as the clock signal width. Separate at least 20 mil from other non-DDR signals. Length matching is set in the unit of byte channel. The length difference of data signal DQ, data strobe DQS and data mask signal DM in each byte channel should be controlled within ±100mil (very important), and the signal length difference of different byte channels Should be controlled within 500 mil. The matching resistance RS in series with the matched DM and DQS is 0-33 Ω, and the value of the parallel matching terminal resistance RT is 25-68 Ω. If the resistance row is used for matching, there should be no other DDR signals in the data resistance row.

5) Clock signal: Take the ground plane as a reference to provide a complete ground plane for the wiring of the entire clock loop and provide a low-impedance path for the loop current. Because it is a differential clock signal, the line width and line spacing should be pre-designed before routing, and the differential impedance requirements of the CPU should be understood, and then routing should be carried out according to this constraint. All DDR differential clock signals must be routed on the key plane to avoid layer-to-layer conversion. The line width and differential spacing need to ensure the 3W principle, the single-line impedance of the signal line should be controlled within 50-60 Ω, and the differential impedance should be controlled within 100-120 Ω. The distance between the clock signal and other signals should be kept at least 20 mil* to prevent interference with other signals. The spacing between serpentine traces should not be less than 20 mil. The RS value of the series terminal resistance is 15～33Ω, and the value of the optional parallel terminal resistance RT is 25～68Ω. (The value of termination resistance should be connected to the resistance when designing the schematic diagram)

6) The decoupling capacitor should be placed near the power pin of the chip in the power supply section. There should be separate layers for power and ground for signals to return with low resistance nearby. The power supply and the ground layer should be punched as much as possible to ensure that the electrical connection is good enough and unblocked.

As long as the above rules and techniques are followed, there will be no problems with the DDR high-speed signals from LAYOUT. In the equal-length processing of each signal, in order to ensure the allowable error of the signal line length, it is possible to deliberately use the long-distance path processing, usually a serpentine line is used to route the line. We often see "equal length wiring". In fact, equal length is not the purpose. The real purpose is to meet the setup and hold time, the same frequency and phase, and the sampling is correct. Equal length is just the easiest way to achieve this purpose, and the line length should be quantitatively analyzed. In terms of online characteristic impedance control, the thickness of the line should generally be required, but the production process and dielectric constant of each board manufacturer are different, so it is necessary to ask the board manufacturer to control the characteristic impedance of the signal line.