PCB News - The main points of high-speed FPGA design circuit board

In the PCB board design, in order to minimize crosstalk, the layout of microstrip lines and strip lines can follow several guidelines. For the dual-strip line layout, the wiring is carried out on the two-layer inner board, and there is a voltage reference surface on both sides. At this time, it is best to use orthogonal wiring technology for all the wires of the adjacent layer board to maximize the distance between the two signal layers. The thickness of the dielectric material, and minimize the distance between each signal layer and its adjacent reference plane, while maintaining the required impedance.

Guidelines for microstrip or stripline wiring

The trace spacing is at least three times the thickness of the dielectric layer between the wiring layers of the circuit board; it is best to use a simulation tool to simulate its behavior in advance.

For critical high-speed networks, use differential instead of single-ended topology to minimize the impact of common mode noise. Within the design limit, try to match the positive and negative pins of the differential signal path.

Reduce the coupling effect of single-ended signals, leave appropriate spacing (more than three times the trace width), or route on different board layers (the adjacent layer wiring is orthogonal to each other). In addition, the use of simulation tools is also a good way to meet the spacing requirements.

Minimize the parallel length between signal termination signals.

Simultaneous conversion noise

When the clock and I/O data rate increase, the number of output conversions decreases accordingly, and the transient current during the discharge and charge period of the signal path increases accordingly. These currents may cause the board-level ground bounce phenomenon, that is, the ground voltage/Vcc rises/drops instantaneously. The large transient current of the non-ideal power supply will cause the instantaneous drop of Vcc (Vcc drop or sag). A few good board design rules are given below to help reduce the influence of these simultaneous conversion noises.

The figure shows the recommended number of signals, power supplies, and ground planes when the available I/O is fully utilized.

Configure the unused I/O pins as output pins and drive them with low voltage to reduce ground bounce.

Try to reduce the number of simultaneous conversion output pins and make them evenly distributed throughout the FPGA I/O section.

When high edge rate is not required, low slew rate is selected for FPGA output.

Insert Vcc between the ground planes of the multilayer PCB board to eliminate the influence of high-speed traces on each layer.

Using all board layers for Vcc and grounding minimizes the resistance and inductance of these planes, thereby providing a low-inductance source with lower capacitance and noise, and returning logic signals on signal layers adjacent to these planes.

Pre-emphasis, equalization

The high-speed transceiver capabilities of the most advanced FPGAs make them highly efficient programmable system-on-chip components, while also presenting unique challenges for circuit board designers. A key issue, especially related to layout, is frequency-dependent transmission loss, which is mainly caused by skin effect and dielectric loss. When high-frequency signals are transmitted on the surface of conductors (such as PCB traces), skin effects will occur due to the self-inductance of the wires. This effect reduces the effective conduction area of the wire and weakens the high-frequency component of the signal. Dielectric loss is caused by the capacitive effect of the dielectric material between the layers. The skin effect is proportional to the square root of frequency, and dielectric loss is proportional to frequency; therefore, dielectric loss is the main loss mechanism of high-frequency signal attenuation.

The higher the data rate, the more serious the skin effect and dielectric loss. For a 1Gbps system, the reduction of the signal level on the link is acceptable, but it is not acceptable for a 6Gbps system. However, current transceivers have transmitter pre-emphasis and receiver equalization functions to compensate for high-frequency channel distortion. They can also enhance signal integrity and relax the limit on trace length. These signal conditioning technologies extend the life of standard FR-4 materials and can support higher data rates. Due to the signal attenuation in the FR-4 material, when working at 6.375Gbps, the allowable trace length is limited to a few inches. The pre-emphasis and equalization function can extend it to more than 40 inches.

Some high-performance FPGAs integrate programmable pre-emphasis and equalization functions, such as Stratix II GX devices, so they can use FR-4 materials, relax the maximum trace length and other layout restrictions, and reduce the cost of the PCB board. The pre-emphasis function can effectively boost the high-frequency components of the signal. The 4-tap pre-emphasis circuit in Stratix II GX can reduce the scattering of signal components (the space spreading from one bit to another). The pre-emphasis circuit can provide a maximum of 500% pre-emphasis. According to the data rate, trace length and link characteristics, each tap can be optimized to a maximum of 16 levels.

The Stratix II GX receiver includes a gain stage and linear equalizer to compensate for signal attenuation. In addition to the input gain stage, the device also allows board designers to have a maximum equalization level of 17dB, and can use any of the 16 equalizer stages to overcome the board loss problem. Equalization and pre-emphasis functions can be used in concert environments or used to individually optimize specific links.

Designers can change the pre-emphasis and equalization stages in Stratix II GX FPGAs while the system is running, or when the card is configured after it is inserted into a backplane or other chassis. This gives the system designer the flexibility to automatically set the pre-emphasis and equalization levels to predetermined values. In addition, depending on which slot on the chassis or backplane the board is inserted into, these values can also be determined dynamically.

EMI issues and debugging

The electromagnetic interference caused by the printed circuit board is directly proportional to the change of current or voltage over time, and the series inductance of the circuit. Efficient circuit board design may minimize EMI, but not necessarily eliminate it completely. Elimination of "intruder" or "hot" signals, and proper reference to the ground plane to send signals, can also help reduce EMI. Finally, using surface mount components that are common in the market today is also a way to reduce EMI.

Debugging and testing complex high-speed PCB designs has become increasingly difficult, because some traditional board debugging methods, such as test probes and "Bed-of-nails" testers, may not be suitable for these designs. This new type of high-speed design can make use of JTAG test tools with in-system programming functions and the built-in self-test function that FPGAs may have. Designers should use the same guidelines to set the JTAG test clock input (TCK) signal as the system clock. In addition, it is also very important to minimize the length of the JTAG scan chain trace between the test data output of one device and the test data input of another device.

To use embedded high-speed FPGA for successful design, you need ample high-speed board design practice and a full understanding of FPGA functions, such as pin arrangement, circuit board materials and stacking, circuit board layout, and terminal mode. The reasonable use of pre-emphasis and equalization functions of the built-in transceiver is also very important. The above points can be combined to achieve a reliable design with stable manufacturability. Careful consideration of all these factors, coupled with correct simulation and analysis, can minimize the possibility of accidents in circuit board prototypes, and will help reduce the pressure on circuit board development projects.