PCB News - High-speed converter PCB design related rules

Q: What are the important PCB board l ayout rules when using high-speed converters PCB?
Answer: In order to ensure that the design performance meets the technical specifications of the data sheet, some guidelines must be followed. First of all, there is a common question: "Should the AGND and DGND ground planes be separated?" The simple answer is: it depends.

The detailed answer is: usually no separation. Because in most cases, separating the ground plane will only increase the inductance of the return current, and it does more harm than good. From the formula V = L (di/dt), it can be seen that as the inductance increases, the voltage noise will increase. And as the switch current increases (because the converter sampling rate increases), the voltage noise will also increase. Therefore, the ground planes should be connected together.
An example is that in some applications, in order to meet the traditional design requirements, it is necessary to place dirty bus power or digital circuits in certain areas. At the same time, it is also affected by size restrictions, making the circuit board unable to achieve good layout division. In this case, separating the ground plane is the key to achieving good performance. However, for the overall design to be effective, these ground planes must be connected together through a bridge or connection point somewhere on the circuit board. Therefore, the connection points should be evenly distributed on a separate ground plane. In the end, there is often a connection point on the PCB board where the return current can pass without causing performance degradation. This connection point is usually located near or below the converter.

When designing power layers, all copper wires that can be used for these layers should be used. If possible, do not let these layers share traces, because additional traces and vias will split the power layer into smaller pieces, which can quickly damage the power layer. The resulting sparse power layer can squeeze the current paths to the places where these paths are most needed, that is, the converter's power pins. Squeezing the current between the via and the trace will increase the resistance, causing a slight voltage drop on the power supply pin of the converter.

Finally, the placement of the power layer is very important. Do not stack high-noise digital power on the analog power layer. Otherwise, although the two are on different layers, they may still be coupled. To minimize the risk of system performance degradation, these types of layers should be separated rather than stacked together as much as possible in the design.
At the same time, discussing printed circuit board (PCB) power transmission system (PDS) design, this task is often overlooked, but it is crucial for system-level analog and digital designers.
The design goal of PDS (Power Transmission System) is to minimize the voltage ripple generated in response to the power supply current demand. All circuits require current, some circuits require a larger amount, and some circuits need to provide current at a faster rate. Adopting a fully decoupled low-impedance power layer or ground layer and a good PCB stackup can minimize the voltage ripple caused by the current demand of the circuit. For example, if the designed switching current is 1A and the impedance of the PDS is 10mΩ, the maximum voltage ripple is 10mV.

First of all, a PCB stack structure that supports larger-layer capacitors should be designed. For example, a six-layer stack may include a top signal layer, a first ground layer, a first power layer, a second power layer, a second ground layer, and a bottom signal layer. It is stipulated that the first ground layer and the first power layer are close to each other in the laminated structure, and the distance between the two layers is 2 to 3 mils, forming an intrinsic layer capacitance. The biggest advantage of this capacitor is that it is free and only needs to be noted in the PCB manufacturing notes. If the power plane must be divided and there are multiple VDD power rails on the same layer, the largest possible power plane should be used. Do not leave holes, but also pay attention to sensitive circuits. This will maximize the capacitance of the VDD layer. If the design allows for additional layers (in this case, from six to eight layers), then two additional ground planes should be placed between the first and second power planes. When the core pitch is also 2 to 3 mils, the inherent capacitance of the laminated structure will be doubled at this time.

For an ideal PCB stackup, decoupling capacitors should be used at the starting point of the power layer and around the DUT. This will ensure that the PDS impedance is low throughout the frequency range. Using several 0.001μF to 100μF capacitors helps to cover this range. It is not necessary to have capacitors everywhere; but the capacitors facing the DUT will break all manufacturing rules. If such severe measures are required, then there are other problems with the circuit.