PCB News - Precautions for the characteristic impedance of pcb proofing

Precautions for the characteristic impedance of PCB proofing

A good laminated structure can effectively control the impedance, and its wiring can form an easy-to-understand and predictable transmission line structure. On-site solution tools can handle such problems well, as long as the number of variables is controlled to a minimum, quite accurate results can be obtained.

However, when three or more signals are stacked together, this is not necessarily the case, and the reason is subtle. The target impedance value depends on the process technology of the device. High-speed CMOS technology can generally reach about 70Ω; high-speed TTL devices generally can reach about 80Ω to 100Ω. Because the impedance value usually has a great influence on noise tolerance and signal switching, it is necessary to be very careful when choosing impedance; the product manual should give guidance on this.
The initial results of the on-site resolution tool may encounter two kinds of problems. The first is the problem of restricted view. The field solution tool only analyzes the influence of nearby traces, and does not consider non-parallel traces on other layers that affect impedance. The on-site solution tool cannot know the details before wiring, that is, when assigning the trace width, but the above-mentioned pair arrangement method can minimize this problem.
It is worth mentioning the influence of partial power planes. The outer circuit board is often crowded with grounded copper wires after wiring, which is beneficial to suppress EMI and balance plating. If only such measures are taken for the outer layer, the laminated structure recommended in this article will have a very small effect on the characteristic impedance.
The effect of using a large number of adjacent signal layers is very significant. Some on-site solution tools cannot find the presence of copper foil, because it can only check the printed lines and the entire layer, so the impedance analysis result is incorrect. When there is metal on the adjacent layer, it acts like a less reliable ground layer. If the impedance is too low, the instantaneous current will be large, which is a practical and sensitive EMI problem.
Another reason for the failure of impedance analysis tools is distributed capacitors. These analysis tools generally cannot reflect the influence of pins and vias (this influence is usually analyzed with a simulator). This effect can be significant, especially on the backplane. The reason is very simple:

The characteristic impedance of PCB proofing can usually be calculated by the following formula: √L/C
Among them, L and C are the inductance and capacitance per unit length respectively.
If the pins are arranged evenly, the additional capacitance will greatly affect the calculation result. The formula will become:
√L/(C+C')
C'is the pin capacitance per unit length.
If the connectors are connected in a straight line as on the backplane, the total line capacitance and the total pin capacitance except the first and last pins can be used. In this way, the effective impedance will be reduced, and may even drop from 80Ω to 8Ω. In order to obtain the effective value, the original impedance value needs to be divided by:
√(1+C'/C)
This calculation is very important for component selection.
When delaying the simulation, the capacitance of the component and the package (and sometimes the inductance should also be included) should be considered. Two issues should be paid attention to. First, the simulator may not be able to simulate the distributed capacitors correctly; secondly, pay attention to the impact of different production conditions on incomplete layers and non-parallel traces. Many on-site solution tools cannot analyze stack distribution without full power or ground planes. However, if there is a ground layer adjacent to the signal layer, the calculated delay will be quite bad, such as a capacitor, there will be the largest delay; if a double-sided board has a lot of ground wires and VCC copper foil on both layers, This situation is even more serious. If the process is not automated, setting up these things in a CAD system will be very messy.
PCB proofing EMC
There are many factors affecting EMC, many of which are usually not analyzed. Even if they are analyzed, it is often after the design is completed, which is too late. The following are some factors that affect EMC:
The slots in the power plane constitute a quarter-wavelength antenna. For occasions where installation grooves are required on metal containers, drilling methods should be used instead.
Inductive components. I once met a designer who followed all the design rules and made simulations, but his circuit board still has a lot of radiation signals. The reason is that there are two inductors placed parallel to each other on the top layer to form a transformer.
Due to the influence of the incomplete ground plane, the low impedance of the inner layer causes a large transient current in the outer layer.
Most of these problems can be avoided by adopting a defensive design. First of all, the correct stack structure and wiring strategy should be made, so that a good start can be made.

The above is the introduction to the characteristic impedance of PCB proofing. Ipcb is also provided to PCB manufacturers and PCB manufacturing technology