Electronic Design - Timing parameters of the basis of clock PCB design

The following is an introduction to the timing parameters of the basis of the clock circuit PCB design:

Some parameters related to timing are Tco, buffer delay, setup time, hold time, setup time margin, hold time margin, propagation delay, maximum/minimum flight time and clock jitter.

1: Tco and buffer delay

Buffer delay refers to the time required for a signal to pass through the buffer to reach a valid voltage output. The buffer delay plus the logic delay inside the digital circuit IC is Tco. Tco also refers to the sum of all delays in the device from the start of the clock trigger to the effective data output device. A measuring load can be directly connected to the end of the digital circuit IC output to determine Tco, and then the time for the signal voltage (Ums) on the load to reach a certain level (usually half of the signal high level). The most common load is a 50Ω resistor or 30pF capacitor. Tco and buffer delay.

2: Setup time, hold time, setup time margin and hold time margin

The setup time and the hold time characterize the input duration of the data before and after the clock edge trigger in the receiving end latch. These two timing parameters are related to the characteristics of the receiver. Before the clock edge is triggered, the data must exist for a period of time, which is the setup time required by the device; and after the clock edge is triggered, the data must be maintained for a period of time in order to be able to be read stably. This is the hold time required by the device. If the duration of the data signal before and after the clock edge trigger exceeds the setup time and the hold time respectively, then the exceeded components are called the setup time margin and the hold time margin respectively. The setup and hold time parameters required for each device can usually be found in the device manual. When designing, the setup time margin and the hold time margin should be increased as much as possible to ensure that the system works normally under the condition of limited changes in the external environment.

3: Propagation delay and flight time

The transmission delay of the signal on the transmission line is called the propagation delay, which is only related to the propagation speed of the signal and the line length. The flight time includes the maximum flight time and the minimum flight time. The maximum flight time is also called the final stable delay, and the minimum flight time is called the earliest switching delay.

4: Clock jitter and clock skew

In practice, the PCB clock signal is often impossible to be an ideal signal, and jitter and offset often occur. Clock jitter refers to the difference between two clock cycles. It is generated internally by the clock and has nothing to do with routing. In a clock oscillator, jitter is caused by the superposition of four noise sources:

1: It is the noise emitted by the crystal itself. Like any resistive device, the crystal will emit thermal noise due to the random movement of internal electrons;

2: It is the noise caused by any mechanical vibration or disturbance of the crystal itself;

3: It is the noise of the amplifier itself, the noise of the amplifier is usually greater than the thermal noise and mechanical noise of the crystal;

4: Power supply noise. Any noise coupled into the power supply terminal will enter the amplifier inside the clock oscillator, and the power supply noise will cause a lot of jitter after being amplified by the amplifier. Power supply noise is difficult to deal with. If the output of an oscillator has large coupled power supply noise, it is said that the immunity of the power supply is very poor. Clock jitter caused by random noise sources is very harmful, and clock jitter caused by power supply noise can cause intermittent fluctuations. Clock jitter can be measured by three methods: spectrum analysis, direct phase measurement, and differential phase measurement. The simplest measurement method is to use differential phase measurement. Clock skew refers to the skew between two identical system clocks, including the skew between multiple outputs of the clock buffer, and the difference between the clock signals at the receiving end and the driving end due to PCB trace errors. Offset. The influence of these factors needs to be considered in the timing design. When designing the PCB, in order to ensure that the data is correctly transmitted and received, all timing parameters must be considered comprehensively, a suitable topology structure must be selected, impedance matching termination and other measures must be adopted to reduce the interference caused by signal integrity to the timing sequence, while satisfying The set-up time constraint and hold-up time constraint required by the system.