Electronic Design - Onlookers high-speed PCB design experience

The learning of high-speed PCB design is a process of "asking without shame" and continuously accumulating experience. Many unexpected gains can be obtained by asking questions and watching other people's questions and answers.

1. When designing high-speed multi-layer PCBs, what is the main basis for the selection of the packaging of resistors and capacitors? Which packages are commonly used, can you give me some examples?

0402 is commonly used in mobile phones; 0603 is commonly used in general high-speed signal modules; the basis is that the smaller the package, the smaller the parasitic parameters. Of course, the same package of different manufacturers has great differences in high-frequency performance.

It is recommended that you use high-frequency special components in key locations.

2. How to consider electromagnetic compatibility EMC/EMI when designing PCB, and what aspects need to be considered? What measures are taken?

EMI/EMC design must consider the location of the device, the arrangement of the PCB stack, the routing of important connections, and the selection of the device at the beginning of the layout.

For example, the location of the clock generator should not be close to the external connector. High-speed signals should go to the inner layer as much as possible. Pay attention to the characteristic impedance matching and the continuity of the reference layer to reduce reflections. The slew rate of the signal pushed by the device should be as small as possible to reduce the height. Frequency components, when choosing a decoupling/bypass capacitor, pay attention to whether its frequency response meets the requirements to reduce noise on the power plane.

In addition, pay attention to the return path of the high-frequency signal current to make the loop area as small as possible (that is, the loop impedance as small as possible) to reduce radiation. The ground can also be divided to control the range of high-frequency noise.

Finally, properly choose the chassis ground between the PCB and the housing.

3. For high-speed multilayer PCBs, what are the appropriate line width settings for power lines, ground lines, and signal lines? What are the common settings? Can you give an example? For example, how to set the working frequency at 300Mhz?

For 300MHz signals, impedance simulation must be performed to calculate the line width and the distance between the line and the ground; the power line needs to determine the line width according to the size of the current. In the mixed-signal PCB, the "line" is generally not used to represent the ground, but the whole Plane, so as to ensure that the loop resistance is minimal, and there is a complete plane under the signal line.

4. When it comes to analog-digital hybrid systems, some people suggest that the electrical layer is divided, and the ground plane should be copper-clad, and some people suggest that the electrical ground layer is divided, and different grounds are connected at the power terminal, but the return path to the signal is far away. How to choose the appropriate method for specific applications?

If there are high-frequency> 20MHz signal lines, and the length and quantity are relatively large, then at least two layers are required for this analog high-frequency signal.

One layer of signal line, one layer of large area ground, and the signal line layer needs to punch enough vias to the ground.

The purpose of this is:

a. For analog signals, this provides a complete transmission medium and impedance matching;

b. The ground plane isolates analog signals from other digital signals;

c. The ground loop is small enough, because you have made a lot of vias, and the ground is a large plane.

5. In the application of high-speed signal chain, there are analog and digital grounds for multiple ASICs. Should the ground be divided or not? What are the existing guidelines? Which effect is better?

There is no conclusion so far. Under normal circumstances, you can refer to the manual of the chip.

The manuals of all ADI hybrid chips recommend you a grounding scheme, some are recommended for common ground, and some are recommended for isolated ground, depending on the chip design.

6. What kind of situation is suitable for serpentine traces in high-speed PCB design? Are there any disadvantages? For example, for differential wiring, the two sets of signals are required to be orthogonal.

Serpentine routing has different functions because of different applications:

a. If the serpentine trace appears in the computer board, it mainly acts as a filter inductance and impedance matching to improve the anti-interference ability of the circuit. The serpentine traces in the computer motherboard are mainly used in some clock signals, such as PCI-Clk, AGPCIK, IDE, DIMM and other signal lines.

b. In the ordinary PCB board, in addition to the role of filter inductance, it can also be used as the inductance coil of the radio antenna and so on. For example, it is used as an inductor in 2.4G walkie-talkies.

c. The wiring length of some signals must be strictly equal. The equal line length of the high-speed digital PCB board is to keep the delay difference of each signal within a range and ensure the validity of the data read by the system in the same cycle (delay When the difference exceeds one clock cycle, the data of the next cycle will be read incorrectly).

For example, there are 13 HUBLinks in the INTELHUB architecture, using a frequency of 233MHz. The lengths must be strictly equal to eliminate the hidden dangers caused by time lag. Winding is the only solution.

Generally, the delay difference is required to not exceed 1/4 clock cycle, and the line delay difference per unit length is also fixed. The delay is related to the line width, line length, copper thickness, and layer structure, but excessively long lines will increase distributed capacitance and distributed inductance., The signal quality has decreased. Therefore, the clock IC pins are generally terminated, but the serpentine trace does not act as an inductance.

On the contrary, the inductance will shift the phase shift of the higher harmonics in the rising edge of the signal, causing the signal quality to deteriorate. Therefore, the serpentine line spacing is required to be at least twice the line width. The smaller the rise time of the signal, the more susceptible to the influence of distributed capacitance and distributed inductance.

d. The serpentine trace acts as a distributed parameter LC filter in some special circuits.